8-Channel/Dual 4-Channel, Low-Leakage, CMOS Analog Multiplexers

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1 9-272; Rev 3; / 8-Channel/Dual -Channel, The / are monolithic, CMOS analog multiplexers (muxes). The 8-channel is designed to connect one of eight inputs to a common output by control of a 3-bit binary address. The dual, - channel is designed to connect one of four inputs to a common output by control of a 2-bit binary address. Both devices can be used as either a mux or a demux. On-resistance is Ω max, and the devices conduct current equally well in both directio. These muxes feature extremely low off leakages (less than 2pA at +2 C), and extremely low on-channel leakages (less than pa at +2 C). The new design offers guaranteed low charge injection (.pc typ) and electrostatic discharge (ESD) protection greater than 2V, per method 3.7. These improved muxes are pin-compatible upgrades for the industry-standard DG8A and DG9A. For similar Maxim devices with lower leakage and charge injection but higher on-resistance, see the MAX328 and MAX329. The / operate from a single +.V to +3V supply or from dual supplies of ±.V to ±2V. All control inputs (whether address or enable) are TTL compatible (+.8V to +2.V) over the full specified temperature range and over the ±.V to ±8V supply range. These parts are fabricated with Maxim s V silicon-gate process. Applicatio Data-Acquisition Systems Test Equipment Military Radios Guidance and Control Systems General Description Sample-and-Hold Circuits Heads-Up Displays Communicatio Systems PBX, PABX Features On-Resistance, <Ω max Traition Time, < On-Resistance Match, <Ω NO-Off Leakage Current, <2pA at +2 C.pC Charge Injection Single-Supply Operation (+.V to +3V) Bipolar-Supply Operation (±.V to ±2V) Plug-In Upgrade for Industry-Standard DG8A/DG9A Rail-to-Rail Signal Handling TTL/CMOS-Logic Compatible ESD Protection >2V, per Method 3.7 PART CPE CSE C/D Ordering Information TEMP RANGE C to +7 C C to +7 C C to +7 C PIN-PACKAGE 6 Plastic DIP 6 Narrow SO Dice* ETE - C to +8 C 6 Thin QFN (mm x mm) EPE - C to +8 C 6 Plastic DIP ESE - C to +8 C 6 Narrow SO EJE - C to +8 C 6 CERDIP MJE - C to +2 C 6 CERDIP** Ordering Information continued at end of data sheet. *Contact factory for dice specificatio. **Contact factory for availability. Pin Configuratio/Functional Diagrams/Truth Tables / TOP VIEW A 6 A NO NO NO2 NO3 NO NO NO6 NO7 NO2 NO3 NO NO NO6 NO7 8 9 CMOS DECODE LOGIC DIP/SO Pin Configuratio/Functional Diagrams/Truth Tables continued at end of data sheet. A A 8-CHANNEL SINGLE-DED MULTIPLEXER Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at , or visit Maxim s website at

2 / ABSOLUTE MAXIMUM RATINGS Voltage Referenced to...-.3v, V...-.3V, 2V Digital Inputs, NO, (Note )...( - 2V) to ( + 2V) or 3mA (whichever occurs first) Continuous Current (any terminal)...3ma Peak Current, NO or (pulsed at ms, % duty cycle max)...ma Note : Continuous Power Dissipation (TA = +7 C) Plastic DIP (derate.3mw/ C above +7 C)...82mW Narrow SO (derate 8.7mW/ C above +7 C)...696mW 6-Pin TQFN (derate 2.3mW/ C above +7 C)...72mW CERDIP (derate.mw/ C above +7 C)...8mW Operating Temperature Ranges MAX33_C... C to +7 C MAX33_E...- C to +8 C MAX33_MJE...- C to +2 C Storage Temperature Range...-6 C to + C Lead Temperature (soldering, sec)...+3 C Signals on NO,,, A, A, or exceeding or are clamped by internal diodes. Limit forward current to maximum current ratings. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated in the operational sectio of the specificatio is not implied. Exposure to absolute maximum rating conditio for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Dual Supplies ( = +V, = -V, = V, V AH = +2.V, V AL = +.8V, T A = T MIN to T MAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX (Note 2) UNITS Analog Signal Range V NO, V - V On-Resistance R ON I NO =.2mA, V = ±V T A = T MIN to T MAX 22 Ω On-Resistance Matching Between Channels R ON I NO =.2mA, V = ±V (Note ). T A = T MIN to T MAX Ω NO-Off Leakage Current (Note ) I NO(OFF) V = +V, V NO = ±V, V = V T A = T MIN to T MAX C, E M na -Off Leakage Current (Note ) I (OFF) V NO = ±V, V = +V, V = V V NO = +V, V = ±V, V = V T A = T MIN to T MAX T A = T MIN to T MAX C, E M C, E M na On Leakage Current (Note ) I (ON) V = ±V, V NO = ±V, sequence each switch on T A = T MIN to T MAX T A = T MIN to T MAX C, E M C, E M na 2

3 ELECTRICAL CHARACTERISTICS Dual Supplies (continued) ( = +V, = -V, = V, V AH = +2.V, V AL = +.8V, T A = T MIN to T MAX, unless otherwise noted.) PARAMETER INPUT Input Current with Input Voltage High Input Current with Input Voltage Low SUPPLY Power-Supply Range Positive Supply Current Negative Supply Current DYNAMIC Traistion Time Break-Before-Make Interval Enable Turn-On Time Enable Turn-Off Time Charge Injection SYMBOL I AH I AL I+ I- t TRANS t OP t ON() t OFF() Q V A = 2.V or V V = V or 2.V, V A = V V = V A = V V = 2.V, V A(ALL) = 2.V V = V or 2.V, V A(ALL) = V, 2.V or V Figure 2 Figure Figure 3 Figure 3 C L = pf, V NO = V, R S = Ω, Figure 6 CONDITIONS T A = T MIN to T MAX T A = T MIN to T MAX T A = T MIN to T MAX T A = T MIN to T MAX T A = T MIN to T MAX MIN TYP MAX (Note 2) ±. ± UNITS µa µa V µa µa µa pc / Off Isolation (Note 6) V ISO V = V, R L = kω, f = khz V = 2.V, Crosstalk Between Channels V CT f = khz, V G = V P-P, -92 db R L = kω, Figure 7 Logic Input Capacitance C IN f = MHz 2 pf f = MHz, NO-Off Capacitance C NO(OFF) V = V NO = V, 3 pf Figure 8 f = MHz, V -Off Capacitance C =.8V, (OFF) T V = V, A = +2 C 6 Figure 8 pf f = MHz, 6 V -On Capacitance C = 2.V, (ON) T V = V, A = +2 C 9 Figure 8 pf -7 db 3

4 / ELECTRICAL CHARACTERISTICS Single Supply ( = +2V, = V, = V, V AH = +2.V, V AL = +.8V, T A = T MIN to T MAX, unless otherwise noted.) Analog Signal Range On-Resistance DYNAMIC PARAMETER Traition Time Enable Turn-On Time Enable Turn-Off Time Charge Injection SYMBOL V NO, V R ON t TRANS t ON() t OFF() Q I NO =.2mA V = 3V or V V NO = 8V, V = V, V IN = 2.V, Figure V INH = 2.V, V INL = V, V NO = V, Figure 3 V INH = 2.V, V INL = V, V NO = V, Figure 3 C L = pf, V NO = V, R S = Ω CONDITIONS MIN TYP MAX (Note 2) UNITS V Ω pc Note 2: The algebraic convention where the most negative value is a minimum and the most positive value a maximum is used in this data sheet. Note 3: Guaranteed by design. Note : R ON = R ON(MAX) - R ON(MIN). Note : Leakage parameters are % tested at the maximum rated hot temperature and guaranteed by correlation at +2 C. Note 6: Worst-case isolation is on channel because of its proximity to the drain pin. Off isolation = 2log V /V NO, where V = output and V NO = input to off switch.

5 Typical Operating Characteristics (, unless otherwise noted.) RON (Ω) ON-RESISTANCE vs. V (DUAL SUPPLIES) ±V ±V ±V ±2V /9 TOC- RON (Ω) 3 2 ON-RESISTANCE vs. V OVER TEMPERATURE (DUAL SUPPLIES) = +V = -V - C +2 C +2 C +8 C /9 TOC-2 RON (Ω) ON-RESISTANCE vs. V (SINGLE SUPPLY) +V +2V +V +2V /9 TOC-3 / V (V) V (V) V (V) ON-RESISTANCE vs. V OVER TEMPERATURE (SINGLE SUPPLY) = +V = V /9 TOC- OFF LEAKAGE vs. TEMPERATURE = +V = -V /9 TOC- ON LEAKAGE vs. TEMPERATURE = +V = -V /9 TOC-6 RON (Ω) C +8 C +2 C - C OFF LEAKAGE (na).. I (OFF) ON LEAKAGE (na).. I (ON). I NO (OFF). V (V) TEMPERATURE ( C) TEMPERATURE ( C) Qj (pc) CHARGE INJECTION vs. V C L = pf = V V (V) ±V +V +2V /9 TOC-7 I+, I- (µa).. SUPPLY CURRT vs. TEMPERATURE I+, V A(ALL) = 2.V I+, V A = V I TEMPERATURE ( C) /9 TOC-8 TRANSITION TIME vs. POWER SUPPLIES 9 R L = kω 8 7 SINGLE SUPPLY 6 3 DUAL SUPPLIES 2 ± ± ± ±2 OR V OR V (SINGLE) (SINGLE) SUPPLY VOLTAGE (V) ttrans (ns) /9 TOC-9

6 / Pin Description PIN NAME FUNCTION DIP/SO THIN QFN DIP/SO THIN QFN,, 6,,, 3 A,, A Address Inputs, 6, A, A Address Inputs Enable 3 3 Negative-Supply Voltage Input 7 2 NO NO Analog Inputs Bidirectional 7 2 NOA NOA Analog Inputs Bidirectional 8 6 Analog Output Bidirectional 8, 9 6, 7 A, B Analog Outputs Bidirectional NO Analog Inputs Bidirectional 3 8 NOB NOB Analog Inputs Bidirectional 3 2 Positive-Supply Voltage Input 2 3 Ground EP EP Exposed Pad Exposed Pad. Connect to. Applicatio Information Operation with Supply Voltages Other than V Using supply voltages less than ±V will reduce the analog signal range. The / switches operate with ±.V to ±2V bipolar supplies or with a +.V to +3V single supply. Connect to when operating with a single supply. Both device types can also operate with unbalanced supplies such as +2V and -V. The Typical Operating Characteristics graphs show typical on-resistance with 2V, V, V, and V supplies. (Switching times increase by a factor of two or more for operation at V.) Overvoltage Protection Proper power-supply sequencing is recommended for all CMOS devices. Do not exceed the absolute maximum ratings, because stresses beyond the listed ratings may cause permanent damage to the devices. Always sequence on first, then, followed by the logic inputs NO and. If power-supply sequencing is not possible, add two small signal diodes in series with supply pi for overvoltage protection (Figure ). Adding diodes reduces the analog signal range to V below and V above, but does not affect the devices low switch resistance and low leakage characteristics. Device operation is unchanged, and the difference between and should not exceed V. V g NO Figure. Overvoltage Protection Using External Blocking Diodes 6

7 Test Circuits/Timing Diagrams Ω Ω A A A A +V -V +V NO NO2-NO7 NOB B -V NOB NOA-NOA kω kω ±V +V ±V +V pf pf LOGIC INPUT OUTPUT +3V V V NO V V t TRANS ON % 9% ON tr < 2 t f < 2 9% t TRANS / Figure 2. Traition Time +V Ω A A NO NO2- kω -V pf LOGIC INPUT +3V V % tr < 2 t f < 2 A -V +V NOB NOA-NOA, NO2B-NOB, A -V OUTPUT V O t ON() V 9% % t OFF() Ω A B kω 3pF -V Figure 3. Enable Switching Time 7

8 / Test Circuits/Timing Diagrams (continued) +2.V Ω A A +V NO- -V kω +V pf LOGIC INPUT OUTPUT +3V V V % 8% t OP tr < 2 t f < 2 Figure. Break-Before-Make Interval +V R S V S CHANNEL SELECT NO A A -V C L = pf LOGIC INPUT +3V V OFF ON OFF IS THE MEASURED VOLTAGE DUE TO CHARGE TRANSFER ERROR Q WH THE CHANNEL TURNS OFF. Q = C L x Figure. Charge Injection 8

9 Test Circuits/Timing Diagrams (continued) R S = Ω V IN NO A A +V nf nf -V R L kω R L = kω R S = Ω NO NO2 A A +V nf nf -V / OFF ISOLATION = 2log V IN CROSSTALK = 2log V IN Figure 6. Off-Isolation Figure 7. Crosstalk +V CHANNEL SELECT A A NO METER IMPEDANCE ANALYZER f = MHz -V Figure 8. NO/ Capacitance 9

10 / Pin Configuratio/Functional Diagrams/Truth Tables (continued) TOP VIEW A A NOA NO2A NO3A A NOA 3 NOB NOA NO2A NO3A 6 2 NO2B NO3B NOB NOA NO2B 7 NB B A 8 9 B NO3B DIP/SO NOB CMOS DECODE LOGIC A A 8-CHANNEL SINGLE-DED MULTIPLEXER A A X X X ON None A A X X ON None 2 3 LOGIC V AL.8V, LOGIC V AH 2.V LOGIC V AL.8V, LOGIC V AH 2.V

11 Ordering Information (continued) PART CPE CSE C/D ETE EPE ESE EJE MJE TEMP RANGE C to +7 C C to +7 C C to +7 C - C to +8 C - C to +8 C - C to +8 C - C to +8 C - C to +2 C *Contact factory for dice specificatio. **Contact factory for availability. PIN-PACKAGE 6 Plastic DIP 6 Narrow SO Dice* 6 Thin QFN (mm x mm) 6 Plastic DIP 6 Narrow SO 6 CERDIP 6 CERDIP** / Pin Configuratio/Functional Diagrams/Truth Tables (continued) TOP VIEW A A A A LOGIC 2 LOGIC 2 NO 2 NOA 2 NOB NO2 3 NO NO2A 3 NO2B NO3 9 NO6 NO3A 9 NO3B NO NO7 NOA A B NOB Thin QFN Thin QFN

12 / Chip Topographies A A A A N.C. NO NO NOA NOB NO2 NO6 NO2A NO2B NO3 N.C.." (2.89mm) NO3A NO3B." (2.89mm) NO N7 NOA NB A B.78" (.98mm).78" (.98mm) N.C. = NO INTERNAL CONNECTION TRANSISTOR COUNT: 22 SUBSTRATE IS INTERNALLY CONNECTED TO Note: On Thin QFN packages connect exposed pad to. TRANSISTOR COUNT: 22 SUBSTRATE IS INTERNALLY CONNECTED TO 2

13 Package Information (The package drawing(s) in this data sheet may not reflect the most current specificatio. For the latest package outline information, go to MARKING PIN # I.D. D D/2 XXXXX e E/2 E (NE-) X e DETAIL A k e D2 C L (ND-) X e D2/2 b L. M C A B E2/2 LC DETAIL B E2 PIN # I.D..3x QFN THIN.EPS / L L C L LC L L. C e e A.8 C C A A3 -DRAWING NOT TO SCALE- PACKAGE OUTLINE, 6, 2, 28, 32L THIN QFN, xx.8mm 2- G 2 PKG. 6L x SYMBOL MIN. NOM. MAX. A A A3 b D E e L N ND NE JEDEC NOTES: REF WHHB MON DIMSIONS BSC..6 BSC. k L.3.. 2L x MIN. NOM. MAX REF WHHC L x MIN. NOM. MAX REF BSC WHHD L x MIN. NOM. MAX REF BSC WHHD DIMSIONING & TOLERANCING CONFORM TO ASME Y.M ALL DIMSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS.. THE TERMINAL # IDTIFIER AND TERMINAL NUMBERING CONVTION SHALL CONFORM TO JESD 9- SPP-2. DETAILS OF TERMINAL # IDTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL # IDTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. EXPOSED PAD VARIATIONS PKG. D2 E2 L DOWN CODES BONDS MIN. NOM. MAX. MIN. NOM. MAX. ±. ALLOWED T ** NO T ** YES T6N ** NO T ** NO T ** YES T ** NO T Y T ** NO T ** NO T ** YES T ** YES T ** NO T ** NO T ** YES T Y T28N ** N T ** NO T ** YES T ** NO T32N ** NO ** SEE MON DIMSIONS TABLE. DIMSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWE.2 mm AND.3 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO22, EXCEPT EXPOSED PAD DIMSION FOR T28-, T28-3 AND T WARPAGE SHALL NOT EXCEED. mm.. MARKING IS FOR PACKAGE ORITATION REFERCE ONLY. 2. NUMBER OF LEADS SHOWN ARE FOR REFERCE ONLY. -DRAWING NOT TO SCALE- PACKAGE OUTLINE, 6, 2, 28, 32L THIN QFN, xx.8mm 2- G 2 2 Maxim cannot assume respoibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licees are implied. Maxim reserves the right to change the circuitry and specificatio without notice at any time. Maxim Integrated Products, 2 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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