Lecture 5 Fault Modeling

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1 Lecture 5 Fault Modeling Why model faults? Some real defects in VLSI and PCB Common fault models Stuck-at faults Single stuck-at faults Fault equivalence Fault dominance and checkpoint theorem Classes of stuck-at faults and multiple faults Transistor faults Summary Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5 ١

2 Why Model Faults? I/O function tests inadequate for manufacturing (functionality versus component and interconnect testing) Real defects (often mechanical) too numerous and often not analyzable A fault model identifies targets for testing A fault model makes analysis possible Effectiveness measurable by experiments Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5 ٢

3 Some Real Defects in Chips Processing defects Missing contact windows Parasitic transistors Oxide breakdown... Material defects Bulk defects (cracks, crystal imperfections) Surface impurities (ion migration)... Time-dependent failures Dielectric breakdown Electromigration... Packaging failures Contact degradation Seal leaks... Ref.: M. J. Howes and D. V. Morgan, Reliability and Degradation - Semiconductor Devices and Circuits, Wiley, Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5 ٣

4 Observed PCB Defects Defect classes Shorts Opens Missing components Wrong components Reversed components Bent leads Analog specifications Digital logic Performance (timing) Occurrence frequency (%) Ref.: J. Bateson, In-Circuit Testing, Van Nostrand Reinhold, Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5 ۴

5 Common Fault Models Single stuck-at faults Transistor open and short faults Memory faults PLA faults (stuck-at, cross-point, bridging) Functional faults (processors) Delay faults (transition, path) Analog faults For more examples, see Section 4.4 (p ) of the book. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5 ۵

6 ٥week Fault Tolerant Digital System Desgin ۶

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11 Z(0 1) = Z(1 0) =0 AND Z(0 1) = Z(1 0) =1 OR ٥week Fault Tolerant Digital System Desgin ١١

12 x x ( NFBF) x ( FBF) ٥week Fault Tolerant Digital System Desgin ١٢

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16 Single Stuck-at Fault Three properties define a single stuck-at fault Only one line is faulty The faulty line is permanently set to 0 or 1 The fault can be at an input or output of a gate Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults 1 0 c s-a-0 a b d e g 1 h i f k Test vector for h s-a-0 fault Faulty circuit value Good circuit value j 0(1) 1(0) Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5 ١۶ 1 z

18 Fault Equivalence Number of fault sites in a Boolean gate circuit = #PI + #gates + # (fanout branches). Fault equivalence: Two faults f1 and f2 are equivalent if all tests that detect f1 also detect f2. If faults f1 and f2 are equivalent then the corresponding faulty functions are identical. Fault collapsing: All single faults of a logic circuit can be divided into disjoint equivalence subsets, where all faults in a subset are mutually equivalent. A collapsed fault set contains one fault from each equivalence subset. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5 ١٨

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Equivalence Example Faults in red removed by equivalence collapsing 20 Collapse

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28 α β ٥week Fault Tolerant Digital System Desgin ٢٨

29 { 00, 01, 10} 01, 10 { 11, 01, 10} 01, 10 ٥week Fault Tolerant Digital System Desgin ٢٩

31 Checkpoints Primary inputs and fanout branches of a combinational circuit are called checkpoints. Checkpoint theorem: A test set that detects all single (multiple) stuck-at faults on all checkpoints of a combinational circuit, also detects all single (multiple) stuck-at faults in that circuit. Total fault sites = 16 Checkpoints ( ) = 10 Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5 ٣١

32 Classes of Stuck-at Faults Following classes of single stuck-at faults are identified by fault simulators: Potentially-detectable fault -- Test produces an unknown (X) state at primary output (PO); detection is probabilistic, usually with 50% probability. Initialization fault -- Fault prevents initialization of the faulty circuit; can be detected as a potentiallydetectable fault. Hyperactive fault -- Fault induces much internal signal activity without reaching PO. Redundant fault -- No test exists for the fault. Untestable fault -- Test generator is unable to find a test. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5 ٣٢

34 Multiple Stuck-at Faults A multiple stuck-at fault means that any set of lines is stuck-at some combination of (0,1) values. The total number of single and multiple stuck-at faults in a circuit with k single fault sites is 3 k -1. A single fault test can fail to detect the target fault if another fault is also present, however, such masking of one fault by another is rare. Statistically, single fault tests cover a very large number of multiple faults. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5 ٣۴

35 Models of fault in PLA-s and PAL-s 1. Permanent constant faults; 2. Short-circuits; 3. Crosspoint Faults ; appearance of CP-s in the AND array;; disappearance of CP-s from the AND array; appearence of CP-s in the OR array; disappearance of CP-s from the OR array. Classical model of fault: constant 1 and 0 (Stuck-at-0, Stuck-at-1, s-a-0, s-a-1) s-a-0 s-a-1 X f X f Short X f1 X f1 X X f2

36 Example. y1 = x1 x2 x3 + x1 x2 x3 + x1 x2 y2 = x1 x2 x3 + x1 x2 x 1 x 2 x 3 0 +V y 1 y 2

37 Permanent constant faults in PLA/PAL-s y1 = x1 x2 x3 + x1 x2 x3 + x1 x2 y2 = x1 x2 x3 + x1 x2 X3 s-a-1fault y1 = x1 x2 y2 = x1 x2 + x1 x2 x3 + x1 x2 + x1 x2 x 1 x 2 x 3 0 +V s-a-1 y 1 y 2

38 Crosspoint Faults Appearance of CP-s to in the AND array Shrinkage fault y1 = x1 x2 x3 + x1 x2 x3 + x1 x2 y2 = x1 x2 x3 + x1 x2 Unnecessary CP y1 = x1 x2 x3 + x1 x2 x3 + x1 x2 x3 y2 = x1 x2 x3 + x1 x2 x3 Unnecessary variable x 1 x 2 x 3 0 +V Carnaugh Map Faultless y2 0 x1 1 x2x Faulty y2 x1 0 1 y 1 y 2 x2x

39 Growth fault Disappearance of CP-s from the AND array y1 = x1 x2 x3 + x1 x2 x3 + x1 x2 y2 = x1 x2 x3 + x1 x2 CP does not exist y1 = x1 x2 x3 + x1 x2 x3 + x1 x2 y2 = x1 x2 x3 + x1 CP does not exist x 1 x 2 x 3 0 +V Carnaugh Map Faultless y2 0 x1 1 x2x Faulty y2 x1 0 1 y 1 y 2 x2x

40 Appearance of a new CP to the OR-array Appearance fault y1 = x1 x2 x3 + x1 x2 x3 + x1 x2 y2 = x1 x2 x3 + x1 x2 Unnecessary CP x 1 x 2 x 3 y1 = x1 x2 x3 + x1 x2 x3 + x1 x2 y2 = x1 x2 x3 + x1 x2 + x1 x2 x3 0 +V Carnaugh Map Faultless y2 0 x1 1 x2x Faulty y2 x1 0 1 y 1 y 2 x2x

41 Disapperance of the CP from the OR-array Disappearance fault y1 = x1 x2 x3 + x1 x2 x3 + x1 x2 y2 = x1 x2 x3 + x1 x2 CP does not exist y1 = x1 x2 x3 + x1 x2 x3 + x1 x2 y2 = x1 x2 x3 +V x 1 x 2 x CP does not exist Carnaugh Map Faultless y2 0 x1 1 x2x Faulty y2 x1 0 1 y 1 y 2 x2x

42 Transistor (Switch) Faults MOS transistor is considered an ideal switch and two types of faults are modeled: Stuck-open -- a single transistor is permanently stuck in the open state. Stuck-short -- a single transistor is permanently shorted irrespective of its gate voltage. Detection of a stuck-open fault requires two vectors. Detection of a stuck-short fault requires the measurement of quiescent current (I DDQ ). Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5 ۴٢

43 Stuck-Open Example Vector 1: test for A s-a-0 (Initialization vector) A B pmos FETs V DD Stuckopen C Vector 2 (test for A s-a-1) Two-vector s-op test can be constructed by ordering two s-at tests 0 1(Z) nmos FETs Good circuit states Faulty circuit states Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5 ۴٣

44 Stuck-Short Example Test vector for A s-a-0 1 A pmos FETs V DD Stuckshort I DDQ path in faulty circuit 0 B C 0 (X) Good circuit state nmos FETs Faulty circuit state Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5 ۴۴

45 Transistor Faults Any transistor can be Stuck-short Also known as stuck-on Stuck-open Also known as stuck-off # fault types: k=2 Example circuit # fault sites: n=4 # single faults =2 4=8 2-input CMOS NOR gate Truth table for fault-free circuit and all possible transistor faults AB Z N 1 stuck-open 1 0 last Z 0 N 1 stuck-short I DDQ N 2 stuck-open 1 last Z 0 0 N 2 stuck-short I DDQ P 1 stuck-open last Z P 1 stuck-short 1 0 I DDQ 0 P 2 stuck-open last Z P 2 stuck-short 1 I DDQ 0 0 VLSI EE141 Test Principles and Architectures Ch. 1 - Introduction - P. 45 A B N 1 Open V DD V SS P 1 P 2 N 2 45 Z

46 Transistor Faults Stuck-short faults cause conducting path from V DD to V SS Can be detect by monitoring steady-state power supply current I DDQ Stuck-open faults cause output node to store last voltage level Requires sequence of 2 vectors for detection detects N 1 stuck-open 2-input CMOS NOR gate Truth table for fault-free circuit and all possible transistor faults AB Z N 1 stuck-open 1 0 last Z 0 N 1 stuck-short I DDQ N 2 stuck-open 1 last Z 0 0 N 2 stuck-short I DDQ P 1 stuck-open last Z P 1 stuck-short 1 0 I DDQ 0 P 2 stuck-open last Z P 2 stuck-short 1 I DDQ 0 0 VLSI EE141 Test Principles and Architectures Ch. 1 - Introduction - P. 46 A B N 1 V DD V SS P 1 P 2 N 2 46 Z

47 Transistor Faults # collapsed faults = 2 T -T S +G S -T P +G P T = number of transistors T S = number of series transistors G S = number of groups of series transistors T P = number of parallel transistors G P = number of groups of parallel transistors For example circuit, # collapsed faults = 6 T=4, T S = 2, G S = 1, T P = 2, & G P = 1 Fault collapsing typically reduces number of transistor faults by 25% to 35% 47 VLSI EE141 Test Principles and Architectures Ch. 1 - Introduction - P. 47

48 Summary Fault models are analyzable approximations of defects and are essential for a test methodology. For digital logic single stuck-at fault model offers best advantage of tools and experience. Many other faults (bridging, stuck-open and multiple stuck-at) are largely covered by stuck-at fault tests. Stuck-short and delay faults and technologydependent faults require special tests. Memory and analog circuits need other specialized fault models and tests. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5 ۴٨

Chapter 2 Fault Modeling

Chapter 2 Fault Modeling Jin-Fu Li Advanced Reliable Systems (ARES) Lab. Department of Electrical Engineering National Central University Jungli, Taiwan Outline Why Model Faults? Fault Models (Faults)