Introduction to VLSI Testing

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1 Introduction to 李昆忠 Kuen-Jong Lee Dept. of Electrical Engineering National Cheng-Kung University Tainan, Taiwan Class

2 Problems to Think How are you going to test A 32 bit adder A 32 bit counter A 32Mb cache memory A transistor CPU A transistor SOC Introduction.2

3 OUTLINE Introduction Fault modeling Fault simulation Test generation Automatic test pattern generation (ATPG) Design for testability Built-in self test Synthesis for testability An eample Introduction.3

4 Basic Concept of Testing Testing: To tell whether a circuit is good or bad VDD /1 Related fields Verification: To verify the correctness of a design Diagnosis: To tell the faulty site Reliability: To tell whether a good system will work correctly or not after some time. Debug: To find the faulty site and try to eliminate the fault Introduction.4

5 Why Studying Testing? Economics! Reduce test cost (enhance profit) Automatic test equipment (ATE) is etremely epensive Shorten time-to-market Market dominating or sharing Guarantee IC quality and reliability Rule of Ten: Cost to detect faulty IC increases by an order of magnitude Defects detected in Cost Wafer Packaged chip Board 1 10 System Field Introduction.5

6 Principle of Testing Input Patterns Stored Correct Response Circuit under Test (CUT) Comparator Output Response Test Result Testing typically consists of Applying set of test stimuli (input patterns, test vectors) to inputs of circuit under test (CUT), and Analyzing output responses The quality of the tested circuits will depend upon the thoroughness of the test vectors Introduction.6

7 Importance of testing N = # transistors in a chip p = prob. (a transistor is faulty) Pf = prob. (the chip is faulty) Pf = 1- (1- p) N If p = 10-6 N = 10 6 Pf = 63.2% Introduction.7

Introduction Integrated Circuits (ICs) have grown in size and compleity since the late 1950 s Small Scale Integration (SSI) Medium Scale Integration (MSI) Large Scale Integration (LSI)

8 Introduction Integrated Circuits (ICs) have grown in size and compleity since the late 1950 s Small Scale Integration (SSI) Medium Scale Integration (MSI) Large Scale Integration (LSI) Very Large Scale Integration (VLSI) Moore s Law: scale of ICs doubles every 18 months Growing size and compleity poses many and new testing challenges S S I M S I LSI VLSI Introduction.8

9 Importance of Testing Moore s Law results from decreasing feature size (dimensions) from 10s of m to 10s of nm for transistors and interconnecting wires Operating frequencies have increased from 100KHz to several GHz Decreasing feature size increases probability of defects during manufacturing process A single faulty transistor or wire results in faulty IC Testing required to guarantee fault-free products Introduction.9

10 Difficulties in Testing Fault may occur anytime - Design - Process - Package - Field Fault may occur at any place Vdd VLSI circuit are large - Most problems encountered in testing are NP-complete I/O access is limited Vss Introduction.10

11 How to do testing From designer s point of view: Circuit modeling Fault modeling Modeling Logic simulation Fault simulation Test generation Design for test Built-in self test ATPG Testable design Synthesis for testability Introduction.11

12 Circuit Modeling Functional model--- logic function - f(1,2,...)=... - Truth table Behavioral model--- functional + timing - f(1,2,...)=..., Delay = 10 Structural model--- collection of interconnected components or elements A B E 1 0 G C D 1 0 F 0 Introduction.12

13 Levels of Structural Description Circuit level C Switch level VDD VDD VDD C 4 B C 3 C 1 C 2 E Gate level A E B G Higher/ System level C D F Introduction.13

14 Fault Modeling The effects of physical defects Most commonly used fault model: Single stuck-at fault A B C D E F G A s-a-1 A s-a-0 E s-a-1 E s-a-0 B s-a-1 B s-a-0 F s-a-1 F s-a-0 C s-a-1 C s-a-0 G s-a-1 G s-a-0 14 faults D s-a-1 D s-a-0 Other fault models: - Break faults, Bridging faults, Transistor stuck-open faults, Transistor stuck-on faults, Delay faults Introduction.14

15 Fault Coverage (FC) FC = # faults detected # faults in fault list Eample: a b c 10 6 stuck-at faults ( a 0,a 1,b 0,b 1,c 0,c 1 ) Test faults detected FC {(0,0)} {(0,1)} {(1,1)} {(0,0),(1,1)} {(1,0),(0,1),(1,1)} c 1 a 1,c 1 a 0,b 0,c 0 a 0,b 0,c 0,c 1 all 16.67% 33.33% 50.00% 66.67% % Introduction.15

16 Wafer Yield (Chip Yield, Yield) Good Chip Faulty Chip Defects Wafer Wafer yield = 12/22 = 0.55 Wafer yield = 17/22 = 0.77 Introduction.16

17 Testing and Quality IC Fabrication Yield: Fraction of good parts Testing Rejects Shipped Parts Quality: Defective parts per million (DPM) Quality of shipped parts is a function of yield Y and the test (fault) coverage T Defect level (DL, reject rate in tetbook): fraction of shipped parts that are defective Introduction.17

18 Defect Level, Yield & Fault Coverage ~ DL = 1 - Y (1-T) DL: defect level Y: yield T: fault coverage Yield (Y) 50% 75% 90% 95% 99% 90% 90% 90% 90% Fault Coverage (T) 90% 90% 90% 90% 90% 90% 95% 99% 99.9% DPM (DL) 67,000 28,000 10,000 5,000 1,000 10,000 5,000 1, Introduction.18

19 Logic simulation To determine how a good circuit should work 1 Given input vectors, determine the normal circuit response A I C A B C E D F B E G C F C C C C 2 I R B R B I C F D C JE E D H E Introduction.19

20 Fault simulation To determine the behavior of faulty circuits A 1 0 B 0 C 0 D E s.a.0 1/0 F 1 1/0 G Given a test vector, determine all faults that are detected by this test vector. Eample: A B C Test vector (1 1) detects { a 0, b 0, c 1 } Introduction.20

21 Test generation Given a fault, identify a test to detect this fault Eample: A B C /0 To detect D s-a-0, D must be set to 1. Thus A=B=1. To propagate fault effect to the primary output E must be 1. Thus C must be 0. Test vector: A=1, B=1, C=0 1 E D 1/0 F Introduction.21

22 Automatic Test Pattern Generation ATPG: Given a circuit, identify a set of test vectors to detect all faults under consideration. Input circuit Form fault list More faults? Yes No Eit Fault dropping Select a fault Test generation Fault simulation Introduction.22

23 Difficulties in Test Generation 1. Reconvergent fanout A B C /1 s-a E D Cannot detect the fault 1 0/1 F Fault detected Introduction.23

24 Difficulties in Test Generation (cont.) 2. Sequential test generation PIs Combinational part POs Y Y J K CK clk Introduction.24

25 Testable Design Design for testability (DFT) ad hoc techniques Scan design Boundary Scan Built-In Self Test (BIST) Random number generator (RNG) Signature Analyzer (SA) Synthesis for Testability Introduction.25

26 Eample of ad hoc Techniques Insert test points MUX T/N Introduction.26

27 Scan Design Original design Modified design PIs POs PIs POs Combinational logic Combinational logic FF FF SFF SFF SO FF Introduction.27 T/N SI SFF

28 Scan Cell Design DI D CK Q Q DI SI N/T (SE) D CK Q Q,SO DI Q DI Q,SO F F SI F Most cell libraries now have scan cells! F T F + F T Introduction.28

29 Scan Register Combinational Circuits Q D Q D Q D Q D SO SI SI SI SI SE CLK Introduction.29

30 Boundary Scan I/O Pad Boundary scan cell Boundary scan path TRST* TDI Sout APPLICATION LOGIC TMS Misc. registers TCK TDO T A P M U X Instruction register Bypass register Sin BIST register Scan register TRST*:Test rest (Optional) TDI: Test data input TD0: Test data output TCK: Test clock TMS: Test mode select Introduction.30

31 Boundary Scan (Cont.) TRST* TRST* TDI Sout APPLICATION LOGIC TDI Sout APPLICATION LOGIC Misc. registers Misc. registers TMS TCK TDO T A P M U X Instruction register Bypass register Sin BIST register Scan register TMS TCK TDO T A P M U X Instruction register Bypass register Sin BIST register Scan register TRST* TRST* TDI Misc. registers Sout APPLICATION LOGIC TDI Misc. registers Sout APPLICATION LOGIC TMS TCK TDO T A P M U X Instruction register Bypass register Sin BIST register Scan register TMS TCK TDO T A P M U X Instruction register Bypass register Sin BIST register Scan register Introduction.31

32 pattern generator Response Analyzer Built-In-Self Test (BIST) Places the job of device testing inside the device itself Generates its own stimulus and analyzes its own response from system mu circuit under test to system BIST Controller good/fail biston bistdone Introduction.32

33 Built-In-Self Test (BIST) (Cont.) Two major tasks - Test pattern generation - Test result compaction Usually implemented by linear feedback shift register F/F F/F F/F Introduction.33

34 Random Number Generator (RNG) F/F F/F F/F F/F (repeat) 1. Generate pseudo random patterns 2. Period is 2 n - 1 Introduction.34

35 Signature Analyzer (SA) Input sequence (8 bits) G P + + Z Time Input stream Register contents Output stream Initial state R Remainder 2 4 Quotient 2 1 Introduction.35

36 Introduction.36 Signature Analyzer (SA) (cont.) A LFSR performs polynomial division Probability of aliasing error = 1/2 n (n: # of FFs) 1 : 1 : Q P G R Q P

37 Memory BIST Architecture Before After di addr wen Memory Module data sys_di sys_addr sys_wen clk hold_l rst_l test_h si se Memory Module data q so Introduction.37

38 Algorithm-Based Pattern Generator Compressor Memory BIST Architecture (Cont.) sys_addr sys_d i sys_wen rst_l clk hold_l test_h di addr wen Memory Module compress_h clk rst si se data q so BIST Circuitry Introduction.38

39 CPU Test Control Architecture Scan_i Scan_en Scan path Scan_o logic rst_l clk hold_l test_h Bist control Memory TDI bist decoder bist_se compressor scan decoder bist_so int_scan mbist decoder TDO TCK TMS TAP Controller IR Introduction.39

40 Problems re-thinking A 32-bit adder --- ATPG A 32-bit counter --- Design for testability + ATPG A 32MB Cache memory --- BIST A transistor CPU --- All test techniques An SOC Introduction.40

41 Conclusions Testing is becoming a major factor in design optimization Conventionally, the designer often optimize one of the three attributes: speed, area, and power. At present, a fourth attribute is considered: Testability. Two major fields in testing ATPG --- Fault simulation --- Test generation Testable design --- Design for testability --- Built-in self-test --- Synthesis for testability Introduction.41

Design for Testability

Design for Testability Outline Ad Hoc Design for Testability Techniques Method of test points Multiplexing and demultiplexing of test points Time sharing of I/O for normal working and testing modes Partitioning