Contributions to the Evaluation of Ensembles of Combinational Logic Gates

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1 Contributions to the Evaluation of Ensembles of Combinational Logic Gates R. P. Ribas, S. Bavaresco, N. Schuch, V. Callegaro,. Lubaszewski, A. I. Reis Institute of Informatics FRGS, Brazil. ISCAS 29 & icroelectronics Journal (Jan.2)

2 OTLINE Introduction and motivation Goals of this work (design specification) Design of combinational blocks (key point) Circuit architecture and operation modes Conclusions and future works 2

3 INTRODCTION ASIC design: standard cells flow (based on cell libraries). Pre-designed cell libraries include in majority combinational gates of different logic functions and with different drive strength options. Handcrafted gate design: pre-defined library composition. Automatic generated cells ( liquid or soft cells ): library-free technology mapping concept (promising possibility for inplace optimization - IPO). Liquid cells (generated by software) must also be pre- characterized for using in IC design flow. 3

4 INTRODCTION On silicon standard cell library validation: for each new process and library composition. Specific test structures: ring oscillators, mixed cell chains, counters,. Tape-outs of benchmarks and application circuits. Full library verification: functionality and performance. Library provider: test engineering cost, use of ATE, time-tomarket, quality, confiability, responsibility and certification, 4

5 OTIVATION Automatic generation provides fast and huge libraries. Specific test structures require handcraft design (design time and costs proportional to the library composition). Ring oscillators and isolated cells under test t_input tc t_output Vdd ring oscillators Vdd Vdd Vdd En isolated cells under test 5

6 OTIVATION Benchmark circuits are not effective for fully functional library verification and validation. ISCAS Benchmarks c7552 i2c_master_top iu mc_top tv8_core wb_conmax_top Small library with 64 combinational cells # cells in the circuit, ,23 6,245 5,594 28,89 # different cells There is no guarantee about complete functional stimuli complete functional stimuli of each different library cell instantiated. 6

7 OBJECTIVE Design a test chip for fully functional verification of each logic gate available in a target library. Obtain a large set of timing and consumption data to validate the delay and power cell model adopted. Allow a fast and low cost test procedure, with minimum external interaction (test vectors generation, use of ATE). Provide a circuit design methodology for automatic generation considering different set of gates for test. At this moment, this work is restricted to combinational gates (the test of storage elements are in study). 7

8 OTLINE Introduction and motivation Goals of this work (design specification) Design of combinational blocks (key point) Circuit architecture and operation modes Conclusions and future works 8

9 COBINATIONAL BLOCKS Two stages can be identified: First: composed by a minimum number of different library cells, directly connected to block inputs (one-level depth). Second: circuit used to recreate the original combinational block input at the block output (multi-level circuit). C W n-inputs C 2 W 2 n-outputs C 3 W 3 C m W m 9

10 COBINATIONAL BLOCKS The number n (inputs and outputs) corresponds to the largest number of inputs in a single cell instantiated in the first stage. The output vector of the first stage W(m..) must provide at least 2 n different values in order to allow the recreation of the input data at the output nodes through the second stage circuit synthesis. It guarantees the full logic stimuli full logic stimuli of each cell instantiated in the first stage (connected to primary block inputs) and the availability of primary input stimuli at the output nodes. C W n-inputs C 2 W 2 n-outputs C 3 W 3 C m W m

11 COBINATIONAL BLOCKS Different combinational blocks are generated until all cells from the library under evaluation have been instantiated in the first stage of (at least) one of these blocks. Once the block input data is reproduced at the block output: the correct behavior of a block is easily verified; different blocks can be cascaded for full logic test of all of them.

12 COBINATIONAL BLOCKS GENERATION First stage: generated automatically (by specific tool) in order to minimize the number of cells instantiated reducing the number of inputs (Wi) of the second stage. Second stage: synthesized by existing mapping engines, considering the expected output data (= primary inputs) and the corresponding values available at W(m..) vector. C W n-inputs C 2 W 2 n-outputs C 3 W 3 C m W m 2

13 IN COBINATIONAL BLOCKS GENERATION: First Stage Example Inputs IN 2 IN 3 Cells NOR2_ [IN,IN2] Library Cells NOR2_ NOR2_ OR3_ NAND2_ OR2_ NAND2_2 NOR2_2 2 different values -bit output (W) A C NOR2_ W OT f IN OT f 2 IN 2 IN 3 OT f 3

14 IN COBINATIONAL BLOCKS GENERATION: First Stage Example Inputs IN 2 IN 3 NOR2_ [IN,IN2] Cells NOR2_ [IN,IN2] Library Cells NOR2_ NOR2_ OR3_ NAND2_ OR2_ NAND2_2 NOR2_2 3 different vectors 2-bit outputs (W2..) A A C NOR2_ C 2 NOR2_ W W 2 OT f IN OT f 2 IN 2 IN 3 OT f 3

15 IN COBINATIONAL BLOCKS GENERATION: First Stage Example Inputs IN 2 IN 3 NOR2_ [IN,IN2] Cells NOR2_ [IN,not_IN2] Library Cells NOR2_ NOR2_ OR3_ NAND2_ OR2_ NAND2_2 NOR2_2 3 different vectors 2-bit outputs (W2..) A A C NOR2_ C 2 NOR2_ W W 2 OT f IN OT f 2 IN 2 IN 3 OT f 3

16 IN COBINATIONAL BLOCKS GENERATION: First Stage Example Inputs IN 2 IN 3 NOR2_ [IN,IN2] Cells NOR2_ [not_in,in2] Library Cells NOR2_ NOR2_ OR3_ NAND2_ OR2_ NAND2_2 NOR2_2 3 different vectors 2-bit outputs (W2..)

17 IN COBINATIONAL BLOCKS GENERATION: First Stage Example Inputs IN 2 IN 3 NOR2_ [IN,IN2] Cells NOR2_ [not_in,not_in2] Library Cells NOR2_ NOR2_ OR3_ NAND2_ OR2_ NAND2_2 NOR2_2 3 different vectors 2-bit outputs (W2..) A A C NOR2_ C 2 NOR2_ W W 2 OT f IN OT f 2 IN 2 IN 3 OT f 3

18 IN COBINATIONAL BLOCKS GENERATION: First Stage Example Inputs IN 2 IN 3 NOR2_ [IN,IN2] Cells NOR2_ [IN2,IN] Library Cells NOR2_ NOR2_ OR3_ NAND2_ OR2_ NAND2_2 NOR2_2 3 different vectors 2-bit outputs (W2..)

19 IN COBINATIONAL BLOCKS GENERATION: First Stage Example Inputs IN 2 IN 3 NOR2_ [IN,IN2] Cells NOR2_ [IN2,not_IN] Library Cells NOR2_ NOR2_ OR3_ NAND2_ OR2_ NAND2_2 NOR2_2 3 different vectors 2-bit outputs (W2..) A A C NOR2_ C 2 NOR2_ W W 2 OT f IN OT f 2 IN 2 IN 3 OT f 3

20 IN COBINATIONAL BLOCKS GENERATION: First Stage Example Inputs IN 2 IN 3 NOR2_ [IN,IN2] Cells NOR2_ [not_in2,in] Library Cells NOR2_ NOR2_ OR3_ NAND2_ OR2_ NAND2_2 NOR2_2 3 different vectors 2-bit outputs (W2..) A A C NOR2_ C 2 NOR2_ W W 2 OT f IN OT f 2 IN 2 IN 3 OT f 3

21 IN COBINATIONAL BLOCKS GENERATION: First Stage Example Inputs IN 2 IN 3 NOR2_ [IN,IN2] Cells NOR2_ [not_in2,not_in] Library Cells NOR2_ NOR2_ OR3_ NAND2_ OR2_ NAND2_2 NOR2_2 3 different vectors 2-bit outputs (W2..)

22 IN COBINATIONAL BLOCKS GENERATION: First Stage Example Inputs IN 2 IN 3 NOR2_ [IN,IN2] Cells NOR2_ [IN,IN3] Library Cells NOR2_ NOR2_ OR3_ NAND2_ OR2_ NAND2_2 NOR2_2 4 different vectors 2-bit outputs (W2..)

23 IN COBINATIONAL BLOCKS GENERATION: First Stage Example Inputs IN 2 IN 3 NOR2_ [IN,IN2] Cells NOR2_ [IN,IN3] OR3_ [IN,IN2,IN3] Library Cells NOR2_ NOR2_ OR3_ NAND2_ OR2_ NAND2_2 NOR2_2 6 different vectors 3-bit outputs (W3..)

24 IN COBINATIONAL BLOCKS GENERATION: First Stage Example Inputs IN 2 IN 3 NOR2_ [IN,IN2] NOR2_ [IN,IN3] Cells OR3_ [IN,IN2,IN3] NAND2_ [IN,IN2] Library Cells NOR2_ NOR2_ OR3_ NAND2_ OR2_ NAND2_2 NOR2_2 8 different vectors ( 2 n ) 4-bit outputs (W4..) A A C NOR2_ C 2 NOR2_ W W 2 OT f IN IN 2 IN 3 A A3 C 3 OR3_ W 3 OT f 2 A C 4 NAND2_ W 4 OT f 3

25 COBINATIONAL BLOCKS GENERATION: First Stage Lower and pper Bounds Single-output cells smallest circuit n cells worst case 2 n - cells.

26 OR2_2 (A,C) OR2_ (B,C) OR3_ (A,B,C) C B A COBINATIONAL BLOCKS GENERATION: COBINATIONAL BLOCKS GENERATION: First Stage Lower and pper Bounds First Stage Lower and pper Bounds

27 OR2_2 (A,C) OR2_ (B,C) OR3_ (A,B,C) C B A COBINATIONAL BLOCKS GENERATION: COBINATIONAL BLOCKS GENERATION: First Stage Lower and pper Bounds First Stage Lower and pper Bounds

28 NAND3_ (C,!B,A) OR3_4 (!C,!B,!A) NOR3_4 (A,C,!B) AND3_ (C,B,!A) NOR3_2 (!C,A,B) AND3_2 (B,A,!C) NOR3_ (A,B,C) C B A COBINATIONAL BLOCKS GENERATION: COBINATIONAL BLOCKS GENERATION: First Stage Lower and pper Bounds First Stage Lower and pper Bounds

29 NAND3_ (C,!B,A) OR3_4 (!C,!B,!A) NOR3_4 (A,C,!B) AND3_ (C,B,!A) NOR3_2 (!C,A,B) AND3_2 (B,A,!C) NOR3_ (A,B,C) C B A COBINATIONAL BLOCKS GENERATION: COBINATIONAL BLOCKS GENERATION: First Stage Lower and pper Bounds First Stage Lower and pper Bounds

30 COBINATIONAL BLOCKS GENERATION: Second Stage Example Inputs 4 output signals from st stage (m=4) Recreate at the block output, the 3 block inputs (n=3) from the 2 n (=8) 4-bit vectors from the st stage 2 3 distinct 4-bit vectors are available, but 2 4 are possible vectors are don t cares and will not happen in fault-free condition, but may happen when block is faulty

31 COBINATIONAL BLOCKS GENERATION: Second Stage Example IN IN 2 IN 3 W W 2 W 3 W 4 f f 2 f 3 IN IN 2 IN 3 A A A A3 A C NOR2_ C 2 NOR2_ C 3 OR3_ C 4 NAND2_ W W 2 W 3 W 4 OT f OT f 2 OT f 3

32 COBINATIONAL BLOCKS GENERATION: Second Stage Example IN IN 2 IN 3 W W 2 W 3 W 4 f f 2 f 3 don tcares IN IN 2 IN 3 A A A A3 A C NOR2_ C 2 NOR2_ C 3 OR3_ C 4 NAND2_ W W 2 W 3 W 4 OT f OT f 2 OT f 3

33 COBINATIONAL BLOCKS GENERATION: Second Stage Example IN IN 2 IN 3 W W 2 W 3 W 4 f f 2 f 3 don tcares single fault detection IN IN 2 IN 3 A A A A3 A C NOR2_ C 2 NOR2_ C 3 OR3_ C 4 NAND2_ W W 2 W 3 W 4 OT f OT f 2 OT f 3

34 COBINATIONAL BLOCKS OPTIIZATION Number of inputs/outputs Number of inputs/outputs: reducing n tends to reduce the number of instantiated cells at the first stage m, and so the W(m..) vector size, which corresponds to the input data of the second stage. It has impact in the second stage size. 34

35 COBINATIONAL BLOCKS OPTIIZATION Number of inputs/outputs: reducing n tends to reduce the number of instantiated cells at the first stage m, and so the W(m..) vector size, which corresponds to the input data of the second stage. It has impact in the second stage size. Cell ordering Cell ordering: the cell list can be ordered by the number of inputs in a decrescent way. aking so, the biggest cells are used in the first blocks, and the inputs of blocks can decrease at each new generation. The CB chain is still allowed. 35

36 COBINATIONAL BLOCKS OPTIIZATION Design : Design 2: 36

37 COBINATIONAL BLOCKS OPTIIZATION design design 2 37 B B4 B7 B B3 B6 B9 B22 B25 B28 B3 B34 B37 B4 B43 B46 B49 B52 B55 B58 B6 B64 B67 B7 B73 Number of Instances B B4 B7 B B3 B6 B9 B22 B25 B28 B3 B34 B37 B4 B43 B46 B49 B52 B55 B58 B6 B64 B67 B7 B73 Number of Instances First Stage design design 2 Combinational Block ID Second Stage Combinational Block ID

38 COBINATIONAL BLOCKS OPTIIZATION 38

39 OTLINE Introduction and motivation Goals of this work (design specification) Design of combinational blocks (key point) Circuit architecture and operation modes Conclusions and future works 39

40 CIRCIT ARCHITECTRE

41 SYNCHRONOS OPERATION ODE External clock signal aximum clock operation frequency: worst case path delay Static and dynamic consumption are easily evaluated Counter (+ K): evaluation can be performed for different transitions + K Ext-CK

SELF-TIED OPERATION ODE Self-timed counter, no external stimuli =Y Ck= / Y Ck= Functional cell verification (self-checking: logic error circuit stops) Aging effects:

42 SELF-TIED OPERATION ODE Self-timed counter, no external stimuli =Y Ck= / Y Ck= Functional cell verification (self-checking: logic error circuit stops) Aging effects: continuous operation (selftimed performance degradation). synchronous mode self-timed mode x In(n..) DFF n n n Q D + K CK Ext-CK n = n Out(n..) In(n..) Out(n..) x y y fault detection

43 OBIST OPERATION ODE No external stimulus needed Delay verification like ring oscillator Delay propagation through a large number of different logic paths Logic and timing errors verification Particular allows open chain test

44 DIAGNOSIS OPERATION ODE Isolate combinational blocks Delay verification: parts of the circuit Can be used in all modes Fault diagnosis

45 DIAGNOSIS OPERATION ODE n s CB n CB 2 CB 3 CB 4 r n In(n..) * + n K(n..) n n Q DFF D CK RST = Ext-CK Out(n..) Interval (ns) Active blocks Period (ns) 5-35 complete chain blocks 3 and block 3.64

46 DIAGNOSIS OPERATION ODE n s CB n CB 2 CB 3 CB 4 r n In(n..) * + n K(n..) n n Q DFF D CK RST = Ext-CK Out(n..) Interval (ns) Active blocks Period (ns) 5-35 complete chain blocks 3 and block 3.64

47 DIAGNOSIS OPERATION ODE n s CB n CB 2 CB 3 CB 4 r n In(n..) * + n K(n..) n n Q DFF D CK RST = Ext-CK Out(n..) Interval (ns) Active blocks Period (ns) 5-35 complete chain blocks 3 and block 3.64

48 DIAGNOSIS OPERATION ODE n ss CB n CB 2 CB 3 CB 4 r n In(n..) * + n K(n..) n n Q DFF D CK RST = Ext-CK Out(n..) Interval (ns) Active blocks Period (ns) 5-35 complete chain blocks 3 and block 3.64

49 INI I/O PINS CONT n inputs: K(n..) n outputs: Out(n..) input clock: Ext-CK output clock: Int-CK initialization: rst control signals of multiplexers (): use of decoder Int-CK In(n..)

LIBRARY CERTIFICATION Business model point-of-view Soft-library vendor Physical testbench Guarantee the correctness of its EDA environment Verify the quality of the generated cells (performance,

50 LIBRARY CERTIFICATION Business model point-of-view Soft-library vendor Physical testbench Guarantee the correctness of its EDA environment Verify the quality of the generated cells (performance, delay and power cell model, reliability, aging effects, ) Improvement of the library generation CAD tool ASIC designer / vendor Exclude errors or faults on silicon due to the cell generators Fabricated in the same die of the ASIC (certification circuit) Overhead

51 CERTIFICATION CIRCIT: OVERHEAD ISCAS Benchmarks c7552 i2c_master_top iu mc_top tv8_core wb_conmax_top # cells in the circuit, ,23 6,245 5,594 28,89 # used different cells sing the proposed testbench: For a library with 64 combinational cells: 45 cells testbench generated Combinational blocks and additional circuitry included 8% overhead, could serve for circuit-level certification For a library 94 combinational cells: 4,48 cells testbench generated

52 CONCLSIONS A test circuit (testbench) for IC design flow and onsilicon for full verification and validation of an entire set of combinational cells. CAD tool was developed in Java in order to automate the generation of combinational blocks. Different operating modes allow a large variety of timing and power measurements.

53 For more information, contact: André I. Reis: Renato P. Ribas:

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