Circuits & Numbers. Symbolic Numbers 28/11/ /11/2012 Digital Synchronous Circuit Digital Number Digital Algebra Digital Function

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1 Circuits & umbers 14/11/2012 Digital Synchronous Circuit Digital umber Digital Algebra Digital Function Symbolic umbers 28/11/2012 Binary Decision Diagram Integer Dichotomy Verification Enumeration 1

0 0 1 1 0 1 1 0 All variables have 0/1 values at all

2 Digital Electronic Circuit Time=0 or even... Time=1 or odd... EBM Images: 1GHz Circuit 10 m 4 Possible Transitions All variables have 0/1 values at all time. Values only change at integer time. clk() t ( t n) n 2

3 Synchronous Traces All registers share the same clock: t Binary values v(t) at all time t Changes v(t- ) v(t+ ) at clock t Synchronous Binary Signals

4 Infinite Binary umber d d0 { d} d( z) d(2) 1. Bit sequence: d d d Integer set: { d} { : d 1} 2 3. Binary series: d( z) d z ( z) adic Integer: d(2) d 2 2 4

5 Ground & Power Ground 0 (0) 0000 g (0) { g} {} g( z) 0 g(2) 0 Power (1) p p p z p 1 z (1) { } ( ) (2)

6 Boolean Gates a{: a 1} b{: b 1} c{: c 1} ca OT c 1 a AD c ab c a b a b OR c ab c a b a b a b XOR c a b c a b a b 2a b 6

7 Synchonous Register o 0 pre( i) o o i 0 0, t1 t i r i r 2 2 r 2i Initial register value is 0. Clock is implicit: t ( t ) All registers share the same isochronous clock. o o i 0 1, t1 t r 1 2i o 1 pre( i) 7

Feedback Unstable! bad = bad bad bad 0 0 0 1 bad 1 2 0,1 Stable?

8 Feedback Unstable! bad = bad bad bad bad 1 2 0,1 Stable? Stable! tog tog tog tog = z( tog) tog tog z tog (01) {1 2 : } z

9 Digital Synchronous Circuit Syntax C( x) x z Gates Fan-out & share Stable feedback Semantics x : y C( x) Variables have binary values at all times Variables change values at integer (i.e. logical) time The value of each variable is an infinite Binary umber Input OT AD XOR REG x t x t 1 t x t x x x' t x x' t x x' t x x' 2 x x' t t t t t z ( x) 0, t xt 1 9

10 Multiplexer m ( cb) ( ca) m c b (1 c ) a m a ( c( ab)) mmux( cba,, ) c 0: m a c 1: m b 10

11 MUX(n) a b f(1,1) f(0,1) f(a,b) f(1,0) f(0,0) MUX(2) cmos MUX(2) 11

12 et-list 2 s = mux(e, d, c) r = mux(m, b, a) m = mux(c, b, a) d = mux(m, a, b) e = mux(r, c, d) Topological Sort 2 m = mux(c, b, a); d = mux(m, a, b); r = mux(m, b, a); e = mux(r, c, d); s = mux(e, d, c); 12

13 Physical Simulation Stable inputs => Stable outputs Delay insensitive stable result ps a b c m d e s r clk time a b c m d e s r a+b+c s+2r

14 Stability An electronic circuit is STABLE if all constant inputs (at logical 0 or 1) eventually forces all variables & outputs to stabilize (at logical 0 or 1). Each Boolean gate is stable within picoseconds. Each register is stable up to the next clock tick. The stable state is unique regardless of delays, for all slow enough clocks. Gates are composed so as to preserve stability: 1. Feed-forward 2. Feedback through a register 3. Stable feedback logic The ZERO DELAY model applies, as long as the clock period is longer than the worst delay. 14

15 Logical Simulation Topological Sort m = mux(c, b, a,) r = mux(m, b, a), d = mux(m, a, b) e = mux(r, c, d) s = mux(e, d, c) a b c m r d e s s+2r

16 Half Adder HalfAdder( ab, ) = ( s, r) { s= aåb r= a Çb } å å a+ b = s + 2c a= a 2 b = b 2 s = s 2 c = c 2 å å s + 2c = a + b s = a + b -2a b c = s= aåb r= açb a b 16

17 Boolean Base x,,, 0,0, x,,,, 0 0 0, x,,, 0, 0, x, mux xmux, 0,, xmux 0, x, mux x, x, 0, x,, 0, xha, 0, xha, FPGA base has all functions 6 2 Circuit designer assembles ~1K IP blocks ASIC base has over ~1K building blocks 17

18 Base x ha z OT ca HalfAdder abs2r Register o 2i 18

19 Counter modulo 2 cm2() i (, s c) { sz( i s) cis} s i x c TRUTH TABLE s zx xis cis ET LIST s i i i t kt 0 1 t1 i s 2 c k t k kt IVARIAT 19

20 Counter Modulo 8 k k k c [0] s [0] 2 c [1] k k k c [1] s [1] 2 c [2] k k k c [2] s [2] 2 c [3] k k k k c [0] S 8 c [3] k k k S s [0] 2 s [1] 4 s [2] IVARIAT 20

21 CM8 cycle i = c[0] s[0] s[1] s[2] c[1] c[2] x[0] x[1] x[2] o

22 Binary n-bit Counter // Binary n bit counter Counter(n:int)(incr:net)= (s:net[n], ovfl:net) { c[0]=incr; // carry in ovfl=c[n]; // carry out for (k<n) (s[k], c[k+1] ) = cm2(c[k]); } Invariant k n t : i s[ k]2 2 o k t k kt kn kt 22

23 Full Adder Icon Invariant a b c s 2r s a b c r a b b c c a Implementations a b c e x,, d r s etlist x ab eab s xc d xc r ed 23

24 BDD Synthesis a b c s r TruthTable LUT Share 24

25 Circuit Simulation p = aå b q= båc s = cå p h= pçq r= båh a b c p q s h r Stable Gates + Stable Composition yield Stable Circuit Delay Invariant Fixpoint Binary Values Sufficient: Synchronous Clock Delay > Critical Path Gate Level Simulators: logical Event Driven Simulators: logical & electrical DSC Vuillemin:

26 Symbolic Execution p a b q b c h p q s c p r b h a b c (01) (0011) ( ) p q h s r (0110) ( ) ( ) ( ) ( ) 26

27 Pause 27

28 Proof by Simulation a b c p= aåb g= açb s= cåp d= cçp r= gåd a b c p= aåb q= båc s= cåp h= pçq r= båh a+ b+ c= s+ 2r s= aåbåc r= abèbcèca = abåbcåca Can (sometimes) verify large circuit through symbolic net-list evaluation over shared DAGs. 28

29 Computational Circuit Proof p = aå b q= båc s= cå p h= pçq r= båh a b c p q s h r V a+ b + c = s + 2r p= aå b g= açb s= cå p d= cçp r= gåd a b c p g s d r V DSC Vuillemin: Topological Sort i 2. Use word length 2 computer 3. Assign magic masks to inputs 4. Evaluate gates in order - i.e. i 5. Compute g2 Boolean results 6. Extract output truth-tables 7. Verify all invariants 29

30 Symbolic Circuit Synthesis s= aåbåc r= açbåbçcåcça Specification s= ( aåb) Åc p= aå b g= açb r= açbå( aåb) Çc s= cå p d= cçp r= gåd Reduce by sharing all equal variables s= ( aåb) Åc r = bå( aåb) Ç( båc) p = aå b q= båc s= cå p h= pçq r= båh DSC Vuillemin:

Digital Synchronous Circuit

Digital Synchronous Circuit. Form Jean Vuillemin École Normale Supérieure, Paris Basic Gates Composition Rules Synthesis 2. Function Indefinite Synchronous Binary Sequences Causal Physical Computations