Digital Synchronous Circuit

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1 Digital Synchronous Circuit. Form Jean Vuillemin École Normale Supérieure, Paris Basic Gates Composition Rules Synthesis 2. Function Indefinite Synchronous Binary Sequences Causal Physical Computations Finite + Causal + Synchronous = DSC DSC Vuillemin

2 Digital Electronic Circuit Time=0 Time= EBM Images GHz Circuit 0 µm 4 Digital Transitions All variables have 0/ values at all time. Values only change at integer time. clk() t = ( t n) n DSC Vuillemin

3 Boolean Gates a = { N: a = } b= { N: b = } c = { N: c = } N N N c = a NOT c t = a t AND c = a b c = a b = ab t t t t t OR c = a b c = a b = a + b ab t t t t t t t XOR c = a b c = a b = a + b 2ab t t t t t t t DSC Vuillemin

4 i r Synchronous Register = = iz t rz t t t Clock is implicit: clk r = z(i) N ( t N) r i = t t r+ 0 = 0 All registers share the same (isochronous) clock. = r = zi All registers have 0 for initial value. r i = t+ t r0 = r = z i r = + zi DSC Vuillemin

5 Multiplexer m = mux(,, c b a) c = 0 m = a t t t c = m = b t t t m = cb + ( c) a t t t t t m = ( c b) ( c a) m = a ( c ( a b)) x = mux( x,0, 0)? x y = mux( x, y, x) x y = mux( x, x, y) < x, >=<,,, x,0, 0, mux > DSC Vuillemin 5

6 8-ways MUX Implement f 3 by LUT (lookup table): f( abc,, ) = T [ a+ 2b+ 4 c] f DSC Vuillemin 6

7 Half Adder sab rab HalfAdder( ab, ) ( s, r) { sab ra b } s a b2ab c t t t t t ab t t t N a a 2 b b 2 N N s s 2 c c 2 N N N N N s 2c a b t t t t ab s2c DSC Vuillemin 7

8 Parallel Increment k x = x 2 = 2 k k k x k y = 2 = c[0] + x k y k n: xn [ ] + cn [ ] = yn [ ] + 2 cn [ + ] x= xn [ ]2 c= cn [ ]2 y= yn [ ]2 n n n n n n I( x) = y = + x I(2 x) = + 2x I( + 2 x) = 2 I( x) 0 = () = = DSC Vuillemin 8

9 Boolean Base < op,..., op > is a Boolean Base if k n f : f ( x,... x ) < x,..., x, op,..., op > n n k < x, >,,, =< x, >,, =< x, >, =< x, 0, ha > =< x, mux > =< x, >=< x, > 0 Nand < x,,, >=< x, ha > a b= ( a b) Nor a b= ( a b) Wolfram s Axiom c = (( a b) c) ( a (( a c) a) DSC Vuillemin 9

10 Full Adder Icon Function s = a b c t t t t r = ab bc ca t t t t t t t a + b + c = s + 2r t t t t t Implementations a b c e x U + d r s x = a b e= a b s = x c d = x c r e d = +U ab 0 a b ab ab ab DSC Vuillemin 0

BDD Synthesis a b c s r 0 0 0 0 0 0 0 0 0 0 0 0 0

11 BDD Synthesis a b c s r Truth Table LUT Share DSC Vuillemin

12 Parallel Add a + b + c = s + 2c a + b + c = s + 2c 2 c0 + a 2 + b 2 = s 2 + c 2 k k k N k k k N k< N k< N k< N DSC Vuillemin

Feedback Unstable Stable z tog = = + N N = = z (0) { 2 : } 2 3 2 bad bad bad = bad 0 0 0 =

13 Feedback Unstable Stable z tog = = + N N = = z (0) { 2 : } bad bad bad = bad = bad = 2 tog = z( tog) tog tog tog tog 0 t+ 2t 2t + = 0 { 0,} = tog = 0 = t Stable? DSC Vuillemin

14 Stability An electronic circuit is STABLE if constant inputs (at logical 0 or ) eventually force all variables to stabilize (at logical 0 or ). Boolean gates are stable within picoseconds. Registers are stable away from clock ticks. The stable state is UNIQUE regardless of delays. Gates are composed to preserve stability:. Feed-forward 2. Feedback through a register 3. Stable feedback logic For all slow enough clocks, all ICs have the SAME digital behavior as the ZERO DELAY model. DSC Vuillemin

15 Analog Simulation ps s = mux(e, d, c) r = mux(m, b, a) m = mux(c, b, a) d = mux(m, a, b) e = mux(r, c, d) a b c m d e s r clk ps a b c m d e s r Transients Stable Glitches Stable DSC Vuillemin

16 Digital Simulation Topological Sort m = mux(c, b, a); d = mux(m, a, b); r = mux(m, b, a); e = mux(r, c, d); s = mux(e, d, c); a b c m d r e s a+b+c s+2r DSC Vuillemin 6

17 Symbolic Proof p = a b p = (00) q = b c h = p q s = c p r = b h a b c = = = (0) (00) (0000) q h s r = = = = (0000) (000000) (0000) (0000) Exhaustive simulation is limited Event driven simulation can help Digital System Proving is a key challenge DSC Vuillemin

18 Counter modulo 2 cm2() i = ( sc, ) { s = z( i s) c = i s} NET LIST s = zx x = i s c = i s s 0 0 i 0 0 x 0 0 c TRUTH TABLE s = i i i t 0 t i = s + 2 c k t k k< t k< t INVARIANT Digital Watch Vuillemin 8

19 Counter Modulo 8 c [0] = s[0] + 2 c [] k t k k< t k< t c [] = s[] + 2 c [2] k t k k< t k< t c [2] = s[2] + 2 c [3] k t k k< t k< t c [0] = S + 8 c [3] k t k k< t k< t S = s[0] + 2 s[] + 4 s[2] t t t t INVARIANT Digital Watch Vuillemin 9

20 CM8 t i s[0] s[] s[2] c[] c[2] x[0] x[] x[2] o Digital Watch Vuillemin 20

21 Digital Systems Why Binary? Physics Information Theory Algebra Automatic Runs Forever No error Cheap Algebra Boolean Algebra 2-adic Numbers Binary Data Flow

Binary Integers n n n l, k: k > l B = B = s utimately constant: w ( s) k l n B n 0 B n B n 2 B n 3 B n 4 [n] {kεn} 0

{0,2} 6 0 0 0 ω 00 ω {,2} 7 0 0 ω 0 ω {0,,2} 8 0 0 0 0 ω 0000 ω {3} n n = Bk 2 = 2 k n k k k n n B n 0 B n B n 2 B n

22 Binary Integers n n n l, k: k > l B = B = s utimately constant: w ( s) k l n B n 0 B n B n 2 B n 3 B n 4 [n] {kεn} ω 0 ω {} ω 0 ω {0} ω 00 ω {} ω 0 ω {0,} ω 000 ω {2} ω 00 ω {0,2} ω 00 ω {,2} ω 0 ω {0,,2} ω 0000 ω {3} n n = Bk 2 = 2 k n k k k n n B n 0 B n B n 2 B n 3 B n 4-0? ω -2 0 ω ω ω ω ω ω ω ω n = ( n+ ) n = + n + n = n+ = n n = n

23 Magic Masks k B B B B B µ 0 0 µ 0 :: µ :: 0000 = µ k k k k k k 0 0 (0) 0 0 (00) ( 0 ) k = B 2 = 2 k 0 n n n n n k 3 µ : k k = = µ k ( 0 ) k 2 3µ 0 = -/3 -/5 -/ µ = =

24 Infinite Binary Number d d = d0 { d} d( z) d(2). Bit sequence: d = d d Integer set: { d} = { N : d N = } 3. Binary series: d( z) = dn z N 4. 2-adic Integer: d(2) = d 2 N N * Real: d( / 2) = d 2 N N Neither unique nor comp utable: = 2 2 n> n

25 Examples 0 = (0) = 0000 = (0) = 000 v (0) { v} 2 vz ( ) v(2) = = = = = 2 z v( ) = = (2) u = = u= () { u} = uz ( ) = z u( ) = = h = { h} = {2 : } Theorem (Adamczewski, Bugeaud 2007) If h(z) is 2-algebraic, then h(/2) is rational or transcendental. hz ( ) 2 = z = is 2-algebrai c. h ( ) = ( ) n z+ hz 2 z+ h ( z is transcendental (over ) )

26 Metrics d = d0 { d} d( z) d(2) Norm 0 = 0, + 2x =, 2x = x 2 Distance dab (, ) = a b = a b a a0 2 n n Limit a 0n n = a (2 ) { a } { a } 0n 0n {} a = { a } n 0n Ultra-metric a+ b max( a, b ) a + b

27 Digital Function Continuous: each output bit depends upon finitely many input bits. Computable: computable primitives composed by finite programs Causal: current output depends upon past inputs (strict or weak) Sequential: causal and finite function of finite circuit/program Real predicates: f continuous constant!

28 Serial Opposite x = + x 28

29 Serial Incr&Decr x = + x x + = x x = x 29

30 2-adic Binary Addition + a b = c s at bt ct st 2ct a 2 b2 c 2 s 2 2 c 2 t t t t t t t t t t sabc 0

Parallel Add a + b + c = s + 2c a + b + c = s + 2c 0 0 0 0 2 N : c +

31 Parallel Add a + b + c = s + 2c a + b + c = s + 2c N : c + a 2 + b 2 = s 2 + c 2 0 k k k N k k k N k< N k< N k< N c0 + A+ B = S 3

32 Serial Add sadd(a,b)= s { (s,r)=fulladd(a,b,c) c=z(r) } t : a + b + c = s + 2r t t t t t c = 0 c = r 0 t+ t a+b+c = s+2r c = 2r a+b = s t a = a 2 b= b2 t t t t c = c 2 s = s 2 t t t t t t t

33 Serial Subtract b b b b b b b b c = +2r a+b +c = d+2r b+b = -? a-b = d

34 Parallel Subtract b b ab ba b' = b c' = c 0 + b' = b c' + a+ b' = s+ c 2 N N a b c0 = s+ c 2 N N 34

35 Time/Space Tradeoffs z=2 z=4 z= 2 z 2 =2 c[2] b[] a[] s[] c[] b[0] a[0] s[0] c[0] a+ b+ c = s+ 2r c = 2r s = a+ b a + 2a + b + 2b + c = s + 2s + 4c c = 4c 0 2 s = a+ b a = u+ v 2 b = w+ x 2 s = ( u+ w) + ( v+ x) 2 35

36 Rhind Papyrus Y

37 Binary Multiplication a b s P = axb + s =2 x =6 x =3 x = x =0 x Maabs (,, ) = a b+ s Ma(2 abs,, ) = Maa (,2 bs, ) Ma(+ 2 a, b, s) = Ma( a,2 b, b + s) Ma(0, b, s) = s Ma(, b, s) = s b 37

38 Binary Series a b az bz ( ) ( ) ( mod 2) Convolution carry-free Product n : n n = [ t B ] n(2) = 2 nz ( ) = t n t n t z t t binary sequence 2-adic integer 2 2 series (z) Series Ring: n n 2 2 Polynomial Rings: [z]/z [z] a b = b a ( ) ( ) a b c = a b c a = a a 0 = 0 ( ) ( ) ( ) a b c = a b a c a b = b a ( ) ( ) a b c = a b c a 0 = a a a = 0 ( a b) = a b za n n = + + za + (mod 2)

39 Boolean Algebra Duality ( a b) = a b ( a b) = a b a b = b a ( ) ( ) a b c = a b c a 0 = a a a = ( ) ( ) ( ) a b c = a b a c 0 a b = b a ( ) ( ) a b c = a b c a 0 = a a a = 0 ( ) ( ) ( ) a b c = a b a c Every finite Boolean Algebra is isomorphic to n for some n.

40 Boolean Ring a b = ( a b) ( a b) 0 = a a a = a a a b = b a ( ) ( ) a b c = a b c a 0 = a a 0 = 0 ( ) ( ) ( ) a b c = a b a c a a b = b ( b c) = ( a b) a 0 = a a a = 0 a a = a a c Every finite Boolean Ring is isomorphic to n n = 2 for some n.

41 Lattice x y x y N : B B = x y d ( xy, ) = ( x y ) H N N N N Hamming Distance a a ( a b) and ( b a) a = b ( a b) and ( b c) ( a b) {} a = {} Partial Order Hypercube H4 a b a, b a b ( c a) and ( c b) ( c a b) ( a c) and ( b c) ( a b c) Distributed Lattice

42 Integer Ring a+ b a + b a b a b a b a b n (2) (2) ( mod 2 ) n (2) (2) ( mod 2 ) n (2) (2) ( mod 2 ) n is isomorphic to / n a b = b a ( ) ( ) a b c = a b c a = a a 0 = 0 ( ) ( ) ( ) a b+ c = a b + a c a+ b = b+ a ( ) ( ) a+ b+ c = a+ b + c a+ 0 = a a a = 0 a = a 2a = n n n 2a 2 a ( mod 2)

43 Hybrid Formulae x v 2 (2 m) x v 2 (2 m) v x2 2 v m xx 2 xx 2 xx 2 v v v x( x) x2 v x( x) x2 x x v ( ) 2 v 2 ab ab ab ab ab ab ab ab ab Many more in Knuth V4!

44 Digital Algebra 2 z 2,,,,, is a Boolean Algebra is a Boolean Ring,,, is a Set Lattice,, is an Integral Domain. za = N N z a, +,-, is an Integral Domain. 2a = 2 N N a 44

Periodic Numbers q 22/7 = 2 00(0) 3 70 48 22 = 0 + 6 = =

45 Periodic Numbers q 22/7 = 2 00(0) = = = Odd denominator rational H(22/7) = 0 H(/7) = 0 H(2/7) = 00 H(/7) = 00 H(-3/7) = 00 H(-5/7) = 00 H(-6/7) = 000 H(-3/7) n num a = a a ( a a ) = a 2 = + 2d 2 0 i i i+ p n n

46 Hensel Division Period Let n and d with d = + 2 d' odd. n Wri te q = = q d N N 2 in binary! nk qd k Algo rithm: n0 = n, qk = nk ( mod 2), n k + =. 2 2 n =(0 =? = = q0qi ( qiqi+ p ) 2 (0) d nk > 0 nk+ < nk Initial part nk < d nk < n k + d nk 0 d n k + 0 i = 0 q 0 Invariant n k = n -k 2 ( mod d) p = order(2, d) p = 2 ( mod d)

Periodic Constant Synthesis 22 = 7 2 00(0) Unary Encoding: 7 reg + 5 not?

47 Periodic Constant Synthesis 22 = (0) Unary Encoding: 7 reg + 5 not? States s[0] s[] s[2] s'[0] s'[] s'[2] o * * * * Binary Encoding: 3 reg +? mux

48 Beyond Addition a = 2 x+ 2a a a 2 ( ) 2x = 3 = (0) x b = x+ a b 3 x = 3 = 2 (0) y = b+ 2b y = x 48

49 Digital Function Continuous: m n m x x ' < 2 fx fx ' < 2 y = f ( x x ) n m 0 m Not continuous: +, Computable: continuous & finitely defined ' 2 z x= ( x ) y = f( x) = ( y ) y = f ( x) n f y = f ( x x ) n n+ 0 n f = 2 f f Sequential: computable with finite memory computed by a finite circuit computed by a finite code + p p Causal: fx fx ' x x ' computed by an infinite circuit 49

50 Sequential Function Causal y = f (x x ) N N 0 N f n n : i( n+ ) j Finite Memory s s = N+ f ( xn, sn) y = f ( x, s ) N y N N State Encoding: Reachable States: rs regs log2 rs f f s i+ m m y i+ m k m s [ ]2 k N = mn k states 2 regs j 50

51 Floor Plan At scale the PA8500 Floor Plan would be wider than France. Vuillemin 204-8

52 Power Vuillemin 204-8

53 Clock Vuillemin 204-8

54 Synchronous circuit Flip Flops Combinational Logic Flip Flops PLL Vuillemin 204-8

55 Trading Time for Space Area = S+T Clk» δt Throughput = o Clk Area = S+2T Clock» 2δT Throughput = 2o Clk Area = 2S+T Clock» δt/2 Throughput = o/2 Clk 55

56 Interconnect Bottleneck λ λ 56

57 Physical Time Speed of light second km/s km Kilometer 0 3 milli sec km/ms m Meter micro sec m/µs cm Centimeter 0 2 nano sec cm/ns mm Millimeter 0 3 pico sec µm/ps µm Micron 0 6 femto sec νm/fs νm Nanometer 0 9 atto sec å/as å Angstrom 0 0 Human Time log 0 scale s/hour s/day s/week s/year ns/s ns/day ns/month ns/year ns/century

58 Digital Synchronous Circuit Syntax Gates <Vdd, Not, And, Or, Xor, Reg> Feed-forward + Stable feedback Semantics Binary Values at all time Discrete Time Zero delay: <In, Not, And, Or, Xor> All Registers have the same unit delay DSC Vuillemin 58

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