DIGITAL LOGIC CIRCUITS

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1 DIGITAL LOGIC CIRCUITS Digital logic circuits BINARY NUMBER SYSTEM electronic circuits that handle information encoded in binary form (deal with signals that have only two values, and ) Digital. computers, watches, controllers, telephones, cameras,... Number.in whatever base Decimal value of the given number Decimal:,998 = x 3 +9x 2 +9x +8x =, =,998 Binary: = x2 +x2 9 +x2 8 +x2 7 +x2 6 +x2 3 +x2 2 +x2 =, =,998 Prof. Emil M. Petriu, School of Electrical Engineering and Computer Science, University of Ottawa

2 Powers of 2 N 2 N Comments ,24 Kilo as 2 is the closest power of 2 to, (decimal) 2, , Hz often used as clock crystal frequency in digital watches... 2,48,576 Mega as 2 2 is the closest power of 2 to,, (decimal)... 3,73,74,824 Giga as 2 3 is the closest power of 2 to,,,(decimal)

3 Negative Powers of 2 N < 2 N = = = = = = = = = = Binary numbers less than Binary Decimal value = x2 - +x2-3 + x2-4 + x2-6 =.7325

4 HEXADECIMAL Binary: <== Decimal Hexadecimal: 7CE = 7x6 2 +2x6 +4x6 = Binary Decimal Hexadecimal A B 2 C 3 D 4 E 5 F

5 LOGIC OPERATIONS AND TRUTH TABLES Digital logic circuits handle data encoded in binary form, i.e. signals that have only two values, and. Binary logic dealing with true and false comes in handy to describe the behaviour of these circuits: is usually associated with false and with true. uite complex digital logic circuits (e.g. entire computers) can be built using a few types of basic circuits called gates, each performing a single elementary logic operation : NOT, AND, OR, NAND, NOR, etc.. Boole s binary algebrais used as a formal / mathematical tool to describe and design complex binary logic circuits.

6 GATES A A NOT A F =A A B A. B A B AND F =A. B A B A + B A B OR F = A + B

7 more GATES A B A. B A B NAND F =A. B A B A +B A B NOR F = A + B

8 and more GATES A B A B A B XOR F = A B A B A B A B EU or XNOR F = A B

9 GATES with more inputs EXAMPLES OF GATES WITH THREE INPUTS A B C A. B. C A+B+C A. B. C A+B+C A B C A B C AND OR F =A. B. C F = A+B+C A B C NAND F =A. B. C A B C NOR F = A+B+C

10 Logic Gate Array that Produces an Arbitrarily Chosen Output A B C F = A. B. C + A. B. C A B C F + A. B. C A. B. C A. B. C A. B. C +A. B. C F A. B. C A B C A B C Sum-of-products form of the logic circuit.

11 BOOLEAN ALGEBRA AND rules A. A = A A. A =. A =. A = A A. B = B. A A. (B. C) =(A. B). C A. (B + C) = A. B + A. C A. B = A + B Proof : A B C A. (B+C) A. B+A. C

12 BOOLEAN ALGEBRA continued OR rules A +A = A A +A = +A = A +A = A +B = B +A A +(B +C) =(A +B) +C A +B. C = (A +B). (A +C) A B C A + B. C (A+B). (A+C) A +B = A. B

13 DeMorgan s Theorem A. B = A + B A + B = A. B A B A. B A + B A + B A. B

14 Simplifying logic functions using Boolean algebra rules A B C Sum-of-products form of the logic function: F=ABC + ABC + ABC + ABC A. B. C A. B. C F A. B. C A. B. C A B C A B C

15 Simplifying logic functions using Boolean algebra rules continued F = ABC + ABC + ABC + ABC F = (ABC + ABC) + (ABC + ABC) F = A(BC + BC) + A ( BC + BC) F = AB( C + C) + AC ( B + B) A B C F = AB + AC A. B F A. C A A

16 Simplifying logic functions using Karnaugh maps Karnaugh map=> graphical representation of a truth table for a logic function. Each line in the truth table corresponds to a square in the Karnaugh map. The Karnaugh map squares are labeled so that horizontally or vertically adjacent squares differ only in one variable. (Each square in the top row is considered to be adjacent to a corresponding square in the bottom row. Each square in the left most column is considered to be adjacent to a corresponding square in the right most column.) Karnaugh map A B C F ()... ()... (2)... (3)... (4)... (5)... (6)... (7)... A B C

17 Simplifying logic functions of 4 variables using Karnaugh maps A B C D F ()... ()... (2)... (3)... (4)... (5)... (6)... (7) (8) (9) () () (2) (3) (4) (5)... A B C D

18 Simplifying logic functions using Karnaugh maps looping The logic expressions for an output can be simplified by properly combining squares (looping) in the Karnaugh maps which contain s. Looping a pair of adjacent s eliminates the variable that appears in both direct and complemented form. A B C F A B () () (2) (3) (4) (5) (6) (7) C AB AC F = AB + AC

19 Simplifying logic functions using Karnaugh maps more looping A B C D F () () (2) (3) (4) (5) (6) (7) (8) (9) () () (2) (3) (4) (5) A B C D Looping aquad of adjacent s eliminates the two variables that appears in both direct and complemented form. F = A B D + AB + BD A B D AB BD

20 DeMorgan s Theorem Equivalent Gate Symbols A. B = A + B A B A. B = A B A+B A + B = A. B A B A+B = A B A. B

21 NAND gate implementation of the sum-of-product logic functions F = AB + AC A B C X = ( X ) NAND gates are faster than ANDs and ORs in most technologies A B C F A F A A

22 ADDING BINARY NUMBERS Adding two bits: Truth table Inputs Outputs A B Carry Sum Sum = A+ B + + A B Half-Adder circuit + Carry (over) + Sum The binary number is equivalent to the decimal 2 Sum Carry Carry = A. B

23 Adding multi-bit numbers: 8 D + 9 D 98 D + Sum A 7 A 6 A 5 A 4 A 3 A 2 A A + B 7 B 6 B 5 B 4 B 3 B 2 B B S 7 S 6 S 5 S 4 S 3 S 2 S S Carry Carry Out A 7 B 7 A 6 B 6 A 5 B 5 A 4 B 4 A 3 B 3 A 2 B 2 A B A B A B A B A B A B A B A B CO CI CO CI CO CI CO CI CO CI CO CI S S S S S S A B A B CO CI CO CI S S Carry In = S 7 S 6 S 5 S 4 S 3 S 2 S S

24 Full Adder Carry Out Bits of the same rank of the two numbers A B CO CI S Sum Carry In Inputs Outputs A B CI CO S A B CI A B CI S CO A. B S= A. B. CI + A. B. CI + A. B. CI + A. B. CI C = A. B + B. CI + A. CI B. CI A. CI

25 HEX-TO-7 SEGMENT DECODER This examples illustrates how a practical problem is analyzed in order to generate truth tables,and then how truth table-defined functions are mapped on Karnaugh maps. B3 B2 B B () () (2) (3) (4) (5) (6) (7) (8) (9) (A) (B) (C) (D) (E) (F) Four-bit machine representation of the hex digits S6 S5 S3 S2 S HEX S6 S5 S S2 S3 7 SEGMENT B3 B2 B B 7-segment display to allow the user see the natural representation of the hex digits. Binary outputs; when such a signal is = then the corresponding segment in the 7-segment display is on (you see it), when the signal is = then the segment is off (you can t see it). The four-bit representation of the hex digits Natural (i.e.as humans write) representation of the hex digits.

26 B3 B2 B B () () (2) (3) (4) (5) (6) (7) (8) (9) (A) (B) (C) (D) (E) (F) S S S S S S6 S2 S6 S2 S6 S2 S6 S2 S6 S2 S5 S3 S5 S3 S5 S3 S5 S3 S5 S3 S S S S S S6 S2 S6 S2 S6 S2 S6 S2 S6 S2 S5 S3 S5 S3 S5 S3 S5 S3 S5 S3 S S S S S S6 S2 S6 S2 S6 S2 S6 S2 S6 S2 S5 S3 S5 S3 S5 S3 S5 S3 S5 S3 S We are developing ad-hoc binary-hex logic expressions used just for our convenience in the problem analysis process. Each expression will enumerate only those hex digits when the specific display-segment is on : S = A+C+E+F S2 = A+D S3 = A+B+D = B+C+D+E S5 = A+B+C+D+E+F S6 = A+B+C+E+F = A+B+D+E+F S6 S2 S5 S3

27 Hex-to-7 segment B3 B2 B B () () (2) (3) (4) (5) (6) (7) (8) (9) (A) (B) (C) (D) (E) (F) S = A+C+E+F S2 = A+D S3 = A+B+D = B+C+D+E S5 = A+B+C+D+E+F S6 = A+B+C+E+F = A+B+D+E+F B3 B2 B B As we are using ad-hoc binary-hex logic equations, (i.e. binary S outputs as functions of hex variables) it will useful in this case to have hex-labeled Karnaugh map, instead of the usual 2-D (i.e. two dimensional) binary labeled K maps. This will allow for a more convenient mapping of the binary-hex logic equations onto the K-maps. 4 C 8 5 D F B 2 6 E A

28 Hex-to-7 segment B3 B2 S B3 B2 S2 Mapping the ad-hoc binary-hex logic equations onto Karnaugh maps: B B B B B3 B2 B B 4 C 8 5 D F B B3 B2 S3 B3 B2 2 6 E A B B B B S = A+C+E+F S2 = A+D S3 = A+B+D = B+C+D+E

29 Hex-to-7 segment B3 B2 S5 B3 B2 S6 B3 B2 B B 4 C 8 5 D F B 2 6 E A B B B3 B2 B B S5 = A+B+C+D+E+F S6 = A+B+C+E+F = A+B+D+E+F B B

30 SYSTEMS of LOGIC FUNCTIONS 2- bit Comparator A A B B F F 2 F 3 () () (2) (3) (4) (5) (6) (7) (8) (9) () () (2) (3) (4) (5) Compare two 2-bit numbers: A=B F = Σ(,5,,5) A>B F 2 = Σ(4,8,9,2,3,4) A<B F 3 = Σ(,2,3,6,7,)

31 2- bit Comparator A=B F = Σ(,5,,5) A A B B AA BB F = when both numbers, A and B, are equal which happens when all their bits of the same order are identical, i.e. A = B AND A = B F= (A B) (A B)

32 2- bit Comparator A<B F 3 = Σ(,2,3,6,7,) A A B B AA BB F3= ABB + AB + AAB

33 2- bit Comparator A A A>B F 2 = Σ(4,8,9,2,3,4) AA BB B B F2 = F + F3 AA BB F +F 3 AA BB F AA BB F 3

34 2- bit Comparator F= (A B) (A B) F2 = F + F3 B B A A F3 = ABB+AB+AAB A B F= (A B) (A B) A B F2 = F + F3 F3 = ABB+AB+AAB

35 3-to-8 Decoder A B C F A B C F F F2 F3F4 F5F6 F7 () () (2) (3) (4) (5) (6) (7) F F2 F3 F4 F5 F6 F7

36 3-to-8 Decoder (74 38) E A B C F A B C EFF F2 F3 F4 F5 F6 F7 (x) x x x () () (2) (3) (4) (5) (6) (7) F F2 F3 F4 F5 F6 F7

37 BCD-TO-7 SEGMENT DECODER S S6 S2 S5 S3 S6 S5 S3 S2 S 7 SEGMENT BCD B3 B2 B B B3 B2 B B () () (2) (3) (4) (5) (6) (7) (8) (9) (x) (x) (x) (x) (x) (x) B3 B2 B B 4 x 8 5 x x x 2 6 x x Don t Care states/situations. As it is expected that these states are never going to occur, then we may just as well use them as fill-in s in a Karnaugh map if this helps to make larger loopings

38 BCD-to-7 segment S S S S S B3 B2 B B () () (2) (3) (4) (5) (6) (7) (8) (9) (x) (x) (x) (x) (x) (x) S6 S5 S6 S5 S2 S6 S2 S3 S5 S3 S S S2 S6 S2 S3 S5 S3 S = S2 = S3 = S6 S5 S6 S5 S S2 S3 S2 S3 S6 S2 S5 S3 S S6 S2 S5 S3 S6 S5 S S6 S5 = S5 = S6 = = S2 S3 S2 S3

39 BCD-to-7 segment S= B3 B2 B B S x x x x x S= B3 + B2B + B x B3 B2 B B 4 x 8 5 x x x 2 6 x x B3 B2 B B S2= S2 x x x x x x + B2B + B2B S2= B3 + B2 + BB + BB

40 BCD-to-7 segment B3 B2 B B 4 x 8 5 x 9 S3 = x x 2 6 x x = B3 B2 S3 B3 B2 B B x x x x x x B B x x x x x x S3= B3 + BB + B + B2 = B3 + B2B +B2B + B2BB+ BB

41 B3 B2 B B BCD-to-7 segment S5= B3 B2 B B 4 x 8 5 x x x 2 6 x x S5 x x x x x x S6 = B3 B2 B B S6 x x x x x x = B3 B2 B B = B3 + + BB2 x B2B + x x x x x BB S5= + B2B BB S6= B3 + BB + BB2 + B2B

42 MEMORY ELEMENTS: LATCHES AND FLIP-FLOPS R-S Latch (Reset-Set) S = = I I2 S F I I2 F = = S R R= = R= = S R S = = S = = Weird state Set state Reset state Hold state R= = R= =

43 D (Transparent) Latch D S Enable D x Enable R Enable D S R S R When the Enable input is = (i.e. TRUE or HIGH) the information present at the Dinput is stored in the latch and will appear as it is at the output ( => it is like that there is a transparent path from the Dinput to the output)

44 D Latch D S Enable D S R Enable R Enable D S R Hold Hold state Transparent state Hold state

45 Latch Latch 2 Synchronous D Flip-Flop D CLK D Enab. EN D EN2 D Enab. Positive-Edge -Triggered DFlip-Flop D CLK D CLK EN D EN2 Din* Latch is Transparent D = Din* Latch 2is Holding Input data Dmay change Latch is Holding Latch 2 is Transparent = D = Din* Latch is Transparent Changed input data Denter Latch Latch 2 is Holding The state of the flip-flop s output copies input Dwhen the positive edge of the clock CLKoccurs Positive-Edge-Triggered D Flip-Flop

46 Synchronous D Flip-Flop Vcc CLR2 D2 CLK2 PR Connection diagram of the7474 Dual Positive-Edge-Triggered D Flip-Flopswith Preset and Clear CLR D CLK PR GND

47 COUNTERS 4-Bit Synchronous Counter using D Flip-Flops Bit BINARY COUNTER 5 CL 6 CK CL = Σ i. 2i i = CK CL

48 DECIMAL BINARY STATE OF FLIP FLOP INPUTS STATE THE COUNTER (for the next state) 3 2 D3 D2 D D Using D flip-flopshas the distinct advantage of a straightforward definition of the flip-flop inputs: the current state of these inputs is the next state of the counter. The logic equations for all four flip-flop inputs D3, D2, D, anddare derived from this truth table as functions of the current states of the counter s flip-flops: 3, 2,, and Karnaugh maps can be used to simplify these equations. 3 2 Synchronous 4-bit Counter D3 3 2 D2 3 2 D 3 2 D

49 Synchronous 4-bit Counter 3 2 D3 3 2 D2 D3 = D2= D 3 2 D=. +. D= D

50 Synchronous 4-bit Counter CL CK D CLK R D= D=. +. D2= D CLK R D3 = D 2 CLK R 2 D 3 CLK R 3

EE40 Lec 15. Logic Synthesis and Sequential Logic Circuits

EE40 Lec 15. Logic Synthesis and Sequential Logic Circuits EE40 Lec 15 Logic Synthesis and Sequential Logic Circuits Prof. Nathan Cheung 10/20/2009 Reading: Hambley Chapters 7.4-7.6 Karnaugh Maps: Read following before reading textbook http://www.facstaff.bucknell.edu/mastascu/elessonshtml/logic/logic3.html