Adders, subtractors comparators, multipliers and other ALU elements
|
|
- Jocelin Black
- 5 years ago
- Views:
Transcription
1 CSE4: Components and Design Techniques for Digital Systems Adders, subtractors comparators, multipliers and other ALU elements
2 Adders 2
3 Circuit Delay Transistors have instrinsic resistance and capacitance Signals take time to propagate from the input to the output of a gate Sometimes delays are labeled in circuit drawings 3
4 -Bit & Multi-bit Adders Half Adder A C out + S B C out Full Adder A + S B C in Types of multi-bit adders Ripple-carry (slow) Carry-lookahead (faster) Two-level logic adder (even faster) A B C out S = A B C out = AB S C in A B C out S C out Symbol A B N N + S N C in S = A B C in C out = AB + AC in + BC in
5 Ripple-Carry Adder Chain -bit adders together Carry ripples through entire chain Disadvantage: slow A 3 B 3 A 3 B 3 A B A B C out + C + 3 C 29 C + C + C in S 3 S 3 S S Ripple-carry adder delay t ripple = Nt FA where t FA is the delay of a full adder
6 Two-level Logic Adder No matter how many inputs you have, look at the truth table, convert to Kmap, apply the algorithm for two-level logic minimization Very fast adder, but. Beyond 8 inputs, a shockingly large amount of gates! Number of gates increases exponentially Ripple carry adder Carry-lookahead adder (next slide) FAST Two-level logic adder COMPLEX
7 Carry-lookahead adders c4 c3 c2 c c a3 a2 a a b3 b2 b b s3 s2 s s Carries First operand Second operand From the very beginning I can look ahead into the value of carries
8 Carry-lookahead adders Adder with propagate (P) and generate (G) outputs: Ci+ = Ai Bi + Ci (Ai xor Bi) Generate Propagate Ci+ = Gi + Ci Pi The carry at some level is equal to if either the generate signal is equal to one or if the propagate and the previous carry are both
9 Carry-lookahead adders Ci+ = Ai Bi + Ci (Ai xor Bi) Carry a b Sum
10 Carry-lookahead adders Example: 4-bit CLA adder c = G + P c c2 = G + P c c3 = G2 + P2 c2 c4 = G3 + P3 c3 Gi = ai bi Pi = ai xor bi generate propagate All G and P are immediately available, but c are not (except the c). So you need to make substitutions: c = G + P c c2 = G + P (G + P c) c3 = G2 + P2 c2 c4 = G3 + P3 c3 = G + PG + PPc = (derive at home) = (derive at home)
11 Carry-lookahead adders Propagate/Generate circuit (one per each input bit) Ai Bi Ci gate delay 2 gate delays gate delay Carry circuits (implement the equations derived in the previous slide) C P G C P P G P G 3 3 C P P P2 G P P2 G P2 G2 3 Note: this approach of looking ahead for building multi-bit operations is not limited to adders! C P P P2 P3 G P P2 P3 G P2 P3 G2 P3 G3 3
12 Combining Adders Example: connect CLAs in a ripple-carry style (6-bit adder) 4-bit 4-bit 4-bit 4-bit CLA CLA CLA cout CLA Example: connect ripple-carry in CLA style (4-bit adder) B[3:2] A[3:2] S[5:2] S[:8] S[7:4] S[3:] CL logic B[:] A[:] c2 Ripplecarry 2-bit S[3:2] Ripplecarry 2-bit S[:] c Connect carries in a chain cin c2 = G + PG + PPc Where: G = AB G = AB P = A xor B P = A xor B 2
13 Subtractors 3
14 2s complement If N is a positive number, then the negative of N (its 2s complement or N* ) is bit-wise complement plus The most significant bit represent the sign: for positive and for negative N bit can represent [ 2 N ] integer positive numbers In 2s complement, you can represent the interval (2 N (2 N )] 4
15 2s Complement: Examples A 8-bit example (positive) = (complement) (add ) A 5-bit example (negative) = -4 (complement) (add ) 5
16 Subtraction If you are using 4 bit numbers, what is the result of the following equation in 2s complement: y = 4-7 A. B. C. D. E. None of the above 6
17 Detecting Overflow: Method Assuming 4-bit two s complement numbers, one can detect overflow by detecting when the two numbers sign bits are the same but are different from the result s sign bit If the two numbers sign bits are different, overflow is impossible Adding a positive and negative can t exceed the largest magnitude positive or negative Simple circuit overflow = a3 b3 s3 + a3b3s3 sign bits overflow (a) overflow (b) no overflow (c) If the numbers sign bits have the same value, which differs from the result s sign bit, overflow has occurred. 7
18 Detecting Overflow: Method 2 Detect a difference between carry-in to sign bit and carry-out from it Yields a simpler circuit: overflow = c3 xor c4 = c3 c4 + c3 c overflow (a) overflow (b) no overflow (c) If the carry into the sign bit column differs from the carry out of that column, overflow has occurred. 8
19 Subtractor A subtraction between A and B is the same as the sum between the first value and the negative of the second value: (A - B) = A + (-B) Represent numbers in 2s complement and use a normal adder! Symbol A B N N - Y N Implementation A B N N N + Y N
20 Adder/subtractor A3 B3B3' A2 B2B2' A BB' A BB' Sel Sel Sel Sel A B A B A B A B Cout Cin Cout Cin Cout Cin Cout Cin Sel Sum Sum Sum Sum S3 S2 S S Overflow In this schematic addition occurs when Sel signal is: A. True B. False 2
21 More ALU Components 2
22 Comparator: Equality Two numbers are equal if each digit at each position is equal (this is true for any base: decimal, binary, etc). The bit-to-bit equality can be evaluated with the XNOR gate. Symbol Implementation A 3 B 3 A 4 = B 4 A 2 B 2 A Equal Equal B A B
23 Comparator: Less Than If a number A is less than B and you consider the difference A B, this is: negative. So comparing numbers is equivalent to check the sign of the difference. In 2s complement representation, the sign of the result corresponds to: the most significant bit A N B N - N [N-] A < B 5-<23>
24 Shifters Logical shifter: shifts value to left or right and fills empty spaces with s Ex: >> 2 = Ex: << 2 = Arithmetic shifter: same as logical shifter, but on right shift, fills empty spaces with the old most significant bit Ex: >>> 2 = Ex: <<< 2 = Rotator: rotates bits in a circle, such that bits shifted off one end are shifted into the other end Ex: ROR 2 = Ex: ROL 2 = Useful for 2- complement numbers
25 General Shifter Design A 3 A 2 A A shamt : 2 S : Y 3 Based on the value of the selection input (shamt = shift amount) S : Y 2 The chain of multiplexers determines how many bits to shift S : S : Y Example: if S = then Y3 = Y2 = A3 Y = A2 Y = A Y
26 Multiplication of positive binary numbers Generalized representation of multiplication by hand Example: in decimal, 32 * 4 = (3+2)*4 = 3*4 + 2*4 Basically: sum up the partial products (pp) The binary multiplier is based on the same idea: For demo see: 26
27 pp4 pp3 pp2 pp Multiplier design array of AND gates Multiplier Array Style a3 a2 a a b b b2 + (5-bit) b3 + (6-bit) A * P B If the multiplier has two N-bit inputs, how many bits are required for the output? + (7-bit) p7..p Block symbol 27
28 Division of positive binary numbers Repeated subtraction Set quotient to Repeat while dividend >= divisor Subtract divisor from dividend Add to quotient When dividend < divisor: Reminder = dividend uotient is correct For demo see: B A Example: Dividend: ; Divisor: Dividend DIVIDER uotient OUT 28
29 ALU: Arithmetic Logic Unit 29
30 Zero Extend 2 3 Arithmetic Logic Unit Example A N N N B N F 2 A N ALU N Y B N 3 F F 2: Function A & B A B A + B Not used A & ~B A ~B C out + [N-] S A - B Not used N N N N 2 F : Implement the ALU using as few components as possible Y N
31 Transistors Summary of what we have seen so far Boolean algebra Basic gates Logic functions and truth tables Canonical forms (SOP and POS) Two-level logic minimization Kmaps Multiplexers (behavior and how to implement logic functions with them) Decoders (behavior and how to implement logic functions with them) Today: Adders, subtractors, and other ALU components SO FAR: only COMBINATIONAL logic (i.e. no memory elements) 3
32 CSE4: Components and Design Techniques for Digital Systems Sequential Circuit Introduction Latches and Flip-Flops Tajana Simunic Rosing
33 What is a sequential circuit? A circuit whose output depends on current inputs and past outputs A circuit with memory Memory / Time steps x i s i y i Clock y i =f i (S t,x) s i t+ =g i (S t,x) 33
34 Why do we need circuits with memory? Circuits with memory can be used to store data Systems have circuits that run a sequence of tasks Memory Hierarchy Registers Cache Main Memory Hard disk
35 Flight attendant call button Flight attendant call button Press call: light turns on Stays on after button released Press cancel: light turns off Logic circuit to implement this? Call button Cancel button Bit Storage Blue light. Call button pressed light turns on SR latch implementation Call= : sets to and keeps it at Cancel= : resets to Call button Cancel button Bit Storage Blue light 2. Call button released light stays on a Call button S Call button Cancel button Bit Storage Blue light Cancel button R Blue light 3. Cancel button pressed light turns off 35
36 SR Latch Analysis S =, R = : then = and = R N S N2 S =, R = : then = and = R N S N2
37 SR Latch Analysis S =, R = : prev = prev = then = prev Memory! R N R N S N2 S N2 S =, R = : then =, = Invalid State NOT R S N N2
38 What if a kid presses both call and cancel Call but ton Cancel but ton & then releases them? S R If S= and R= at the same time and then released, =? Can also occur also due to different delays of different paths may oscillate and eventually settle to or due to diff. path delay 38 Blue light S R hold not allowed S R t
39 SR Latch Symbol SR stands for Set/Reset Latch Stores one bit of state () Control what value is being stored with S, R inputs Set: Make the output (S =, R =, = ) Reset: Make the output (S =, R =, = ) Hold: Keep data stored (S =, R =, = previous ) SR Latch Symbol R S
40 SR Latch Characteristic Equation To analyze, break the feedback path SR Latch Symbol R (t) R S ' S R (t+ ) S S R (t) (t+ ) S hold X reset (t) X R set X characteristic equation not allowed X (t+ ) = S + R (t) State Diagram 4 SR
41 Add input C Avoiding S=R= Part : Level-Sensitive SR Latch Change C to only after S and R are stable C is usually a clock (CLK) S Level-sensitive SR latch S C R R
42 Clocks Freq GHz GHz GHz MHz MHz Period. ns. ns ns ns ns Clock -- Pulsing signal for enabling latches; ticks like a clock Synchronous circuit: sequential circuit with a clock Clock period: time between pulse starts Above signal: period = 2 ns Clock cycle: one such time interval Above signal shows 3.5 clock cycles Clock duty cycle: time clock is high 5% in this case Clock frequency: /period Above : freq = / 2ns = 5MHz; 42
43 Clock question The clock shown in the waveform below has: ns CLK A. Clock period of 4ns with 25MHz frequency B. Clock duty cycle 75% C. Clock period of ns with GHz frequency D. A. & B. E. None of the above 43
44 Avoiding S=R= Part 2: Level-Sensitive D Latch D C D S D latch S C R R SR latch requires careful design so SR= never occurs D latch helps by inserting the inverter between S & R inputs Inserted inverter ensures R is always the opposite of S when C= 44
45 D Latch Truth Table CLK D R R D S S CLK D X D X S R prev prev
46 D Latch Summary Two inputs: CLK, D CLK: controls when the output changes D (the data input): controls what the output changes to Function When CLK =, D passes through to (transparent) When CLK =, holds its previous value (opaque) (Mostly) avoids invalid case = D Latch Symbol D CLK
47 Level-Sensitive D Latches Assume that data in all latches is initially. Input Y= and Clk transitions from ->. When Clk= again, the stored values in latches are: Y D D2 2 D3 3 D4 4 C C2 C3 C4 Clk Clk_A Clk_B A. =, 2=, 3=, 4= for both clock A & B B. =, 2=, 3=, 4= for clock A =, 2=, 3=, 4= for clock B C. =, 2=, 3=, 4= for both clocks D. More information is needed to determine the answer E. None of the above 47
48 D Flip-Flop Design & Timing Diagram D flip-flop D Dm D latch m Ds D latch s Cm Cs s master servant Clk Flip-flop: Bit storage that stores on the clock edge, not level Master-slave design: master loads when Clk=, then slave when Clk= 48
49 D Flip-Flop: Characteristic Equation D CLK Id D (t) (t+) 2 3 Characteristic Equation (t+) = D(t)
Adders, subtractors comparators, multipliers and other ALU elements
CSE4: Components and Design Techniques for Digital Systems Adders, subtractors comparators, multipliers and other ALU elements Instructor: Mohsen Imani UC San Diego Slides from: Prof.Tajana Simunic Rosing
More informationCSE140: Components and Design Techniques for Digital Systems. Decoders, adders, comparators, multipliers and other ALU elements. Tajana Simunic Rosing
CSE4: Components and Design Techniques for Digital Systems Decoders, adders, comparators, multipliers and other ALU elements Tajana Simunic Rosing Mux, Demux Encoder, Decoder 2 Transmission Gate: Mux/Tristate
More informationALU, Latches and Flip-Flops
CSE14: Components and Design Techniques for Digital Systems ALU, Latches and Flip-Flops Tajana Simunic Rosing Where we are. Last time: ALUs Plan for today: ALU example, latches and flip flops Exam #1 grades
More informationCSE140: Components and Design Techniques for Digital Systems. Logic minimization algorithm summary. Instructor: Mohsen Imani UC San Diego
CSE4: Components and Design Techniques for Digital Systems Logic minimization algorithm summary Instructor: Mohsen Imani UC San Diego Slides from: Prof.Tajana Simunic Rosing & Dr.Pietro Mercati Definition
More informationCS 140 Lecture 14 Standard Combinational Modules
CS 14 Lecture 14 Standard Combinational Modules Professor CK Cheng CSE Dept. UC San Diego Some slides from Harris and Harris 1 Part III. Standard Modules A. Interconnect B. Operators. Adders Multiplier
More informationCarry Look Ahead Adders
Carry Look Ahead Adders Lesson Objectives: The objectives of this lesson are to learn about: 1. Carry Look Ahead Adder circuit. 2. Binary Parallel Adder/Subtractor circuit. 3. BCD adder circuit. 4. Binary
More informationChapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1>
Chapter 5 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 5 Chapter 5 :: Topics Introduction Arithmetic Circuits umber Systems Sequential Building
More informationELEN Electronique numérique
ELEN0040 - Electronique numérique Patricia ROUSSEAUX Année académique 2014-2015 CHAPITRE 3 Combinational Logic Circuits ELEN0040 3-4 1 Combinational Functional Blocks 1.1 Rudimentary Functions 1.2 Functions
More informationCSE140: Components and Design Techniques for Digital Systems. Midterm Information. Instructor: Mohsen Imani. Sources: TSR, Katz, Boriello & Vahid
CSE140: Components and Design Techniques for Digital Systems Midterm Information Instructor: Mohsen Imani Midterm Topics In general: everything that was covered in homework 1 and 2 and related lectures,
More informationCombinational Logic. By : Ali Mustafa
Combinational Logic By : Ali Mustafa Contents Adder Subtractor Multiplier Comparator Decoder Encoder Multiplexer How to Analyze any combinational circuit like this? Analysis Procedure To obtain the output
More informationMidterm Exam Two is scheduled on April 8 in class. On March 27 I will help you prepare Midterm Exam Two.
Announcements Midterm Exam Two is scheduled on April 8 in class. On March 27 I will help you prepare Midterm Exam Two. Chapter 5 1 Chapter 3: Part 3 Arithmetic Functions Iterative combinational circuits
More informationChapter 4. Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. elements. Dr.
Chapter 4 Dr. Panos Nasiopoulos Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. Sequential: In addition, they include storage elements Combinational
More information14:332:231 DIGITAL LOGIC DESIGN
4:332:23 DIGITAL LOGIC DEIGN Ivan Marsic, Rutgers University Electrical & Computer Engineering Fall 23 Lecture #4: Adders, ubtracters, and ALUs Vector Binary Adder [Wakerly 4 th Ed., ec. 6., p. 474] ingle
More informationLecture 7: Sequential Networks
CSE 140: Components and Design Techniques for Digital Systems Lecture 7: Sequential Networks CK Cheng Dept. of Computer Science and Engineering University of California, San Diego 1 Part II: Sequential
More informationHardware Design I Chap. 4 Representative combinational logic
Hardware Design I Chap. 4 Representative combinational logic E-mail: shimada@is.naist.jp Already optimized circuits There are many optimized circuits which are well used You can reduce your design workload
More informationPG - TRB UNIT-X- DIGITAL ELECTRONICS. POLYTECHNIC-TRB MATERIALS
SRIMAAN COACHING CENTRE-PG-TRB-PHYSICS- DIGITAL ELECTRONICS-STUDY MATERIAL-CONTACT: 8072230063 SRIMAAN PG - TRB PHYSICS UNIT-X- DIGITAL ELECTRONICS POLYTECHNIC-TRB MATERIALS MATHS/COMPUTER SCIENCE/IT/ECE/EEE
More informationCPE100: Digital Logic Design I
Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu CPE100: Digital Logic Design I Final Review http://www.ee.unlv.edu/~b1morris/cpe100/ 2 Logistics Tuesday Dec 12 th 13:00-15:00 (1-3pm) 2 hour
More informationChapter 5 Arithmetic Circuits
Chapter 5 Arithmetic Circuits SKEE2263 Digital Systems Mun im/ismahani/izam {munim@utm.my,e-izam@utm.my,ismahani@fke.utm.my} February 11, 2016 Table of Contents 1 Iterative Designs 2 Adders 3 High-Speed
More informationReview for Final Exam
CSE140: Components and Design Techniques for Digital Systems Review for Final Exam Mohsen Imani CAPE Please submit your evaluations!!!! RTL design Use the RTL design process to design a system that has
More informationDesign of Sequential Circuits
Design of Sequential Circuits Seven Steps: Construct a state diagram (showing contents of flip flop and inputs with next state) Assign letter variables to each flip flop and each input and output variable
More informationBoolean Algebra and Digital Logic 2009, University of Colombo School of Computing
IT 204 Section 3.0 Boolean Algebra and Digital Logic Boolean Algebra 2 Logic Equations to Truth Tables X = A. B + A. B + AB A B X 0 0 0 0 3 Sum of Products The OR operation performed on the products of
More informationFundamentals of Digital Design
Fundamentals of Digital Design Digital Radiation Measurement and Spectroscopy NE/RHP 537 1 Binary Number System The binary numeral system, or base-2 number system, is a numeral system that represents numeric
More informationPhiladelphia University Student Name: Student Number:
Philadelphia University Student Name: Student Number: Faculty of Engineering Serial Number: Final Exam, First Semester: 2017/2018 Dept. of Computer Engineering Course Title: Logic Circuits Date: 29/01/2018
More informationDIGITAL TECHNICS. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute
DIGITAL TECHNICS Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 4. LECTURE: COMBINATIONAL LOGIC DESIGN: ARITHMETICS (THROUGH EXAMPLES) 2016/2017 COMBINATIONAL LOGIC DESIGN:
More informationDigital Logic: Boolean Algebra and Gates. Textbook Chapter 3
Digital Logic: Boolean Algebra and Gates Textbook Chapter 3 Basic Logic Gates XOR CMPE12 Summer 2009 02-2 Truth Table The most basic representation of a logic function Lists the output for all possible
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 6 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT2: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 4 Following the slides of Dr. Ahmed H. Madian محرم 439 ه Winter 28
More informationLogic and Computer Design Fundamentals. Chapter 5 Arithmetic Functions and Circuits
Logic and Computer Design Fundamentals Chapter 5 Arithmetic Functions and Circuits Arithmetic functions Operate on binary vectors Use the same subfunction in each bit position Can design functional block
More informationUnit II Chapter 4:- Digital Logic Contents 4.1 Introduction... 4
Unit II Chapter 4:- Digital Logic Contents 4.1 Introduction... 4 4.1.1 Signal... 4 4.1.2 Comparison of Analog and Digital Signal... 7 4.2 Number Systems... 7 4.2.1 Decimal Number System... 7 4.2.2 Binary
More informationEE40 Lec 15. Logic Synthesis and Sequential Logic Circuits
EE40 Lec 15 Logic Synthesis and Sequential Logic Circuits Prof. Nathan Cheung 10/20/2009 Reading: Hambley Chapters 7.4-7.6 Karnaugh Maps: Read following before reading textbook http://www.facstaff.bucknell.edu/mastascu/elessonshtml/logic/logic3.html
More informationCMSC 313 Lecture 17. Focus Groups. Announcement: in-class lab Thu 10/30 Homework 3 Questions Circuits for Addition Midterm Exam returned
Focus Groups CMSC 33 Lecture 7 Need good sample of all types of CS students Mon /7 & Thu /2, 2:3p-2:p & 6:p-7:3p Announcement: in-class lab Thu /3 Homework 3 Questions Circuits for Addition Midterm Exam
More informationAdders allow computers to add numbers 2-bit ripple-carry adder
Lecture 12 Logistics HW was due yesterday HW5 was out yesterday (due next Wednesday) Feedback: thank you! Things to work on: ig picture, ook chapters, Exam comments Last lecture dders Today Clarification
More informationCombinational Logic. Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C.
Combinational Logic ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Combinational Circuits
More informationCOE 202: Digital Logic Design Combinational Circuits Part 2. Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:
COE 202: Digital Logic Design Combinational Circuits Part 2 Dr. Ahmad Almulhem Email: ahmadsm AT kfupm Phone: 860-7554 Office: 22-324 Objectives Arithmetic Circuits Adder Subtractor Carry Look Ahead Adder
More informationCS61C : Machine Structures
CS 61C L15 Blocks (1) inst.eecs.berkeley.edu/~cs61c/su05 CS61C : Machine Structures Lecture #15: Combinational Logic Blocks Outline CL Blocks Latches & Flip Flops A Closer Look 2005-07-14 Andy Carle CS
More informationALU A functional unit
ALU A functional unit that performs arithmetic operations such as ADD, SUB, MPY logical operations such as AND, OR, XOR, NOT on given data types: 8-,16-,32-, or 64-bit values A n-1 A n-2... A 1 A 0 B n-1
More informationSystems I: Computer Organization and Architecture
Systems I: Computer Organization and Architecture Lecture 6 - Combinational Logic Introduction A combinational circuit consists of input variables, logic gates, and output variables. The logic gates accept
More informationLatches. October 13, 2003 Latches 1
Latches The second part of CS231 focuses on sequential circuits, where we add memory to the hardware that we ve already seen. Our schedule will be very similar to before: We first show how primitive memory
More informationARITHMETIC COMBINATIONAL MODULES AND NETWORKS
ARITHMETIC COMBINATIONAL MODULES AND NETWORKS 1 SPECIFICATION OF ADDER MODULES FOR POSITIVE INTEGERS HALF-ADDER AND FULL-ADDER MODULES CARRY-RIPPLE AND CARRY-LOOKAHEAD ADDER MODULES NETWORKS OF ADDER MODULES
More informationLecture 7: Logic design. Combinational logic circuits
/24/28 Lecture 7: Logic design Binary digital circuits: Two voltage levels: and (ground and supply voltage) Built from transistors used as on/off switches Analog circuits not very suitable for generic
More informationCS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c/su05 CS61C : Machine Structures Lecture #15: Combinational Logic Blocks 2005-07-14 CS 61C L15 Blocks (1) Andy Carle Outline CL Blocks Latches & Flip Flops A Closer Look CS
More informationBinary addition by hand. Adding two bits
Chapter 3 Arithmetic is the most basic thing you can do with a computer We focus on addition, subtraction, multiplication and arithmetic-logic units, or ALUs, which are the heart of CPUs. ALU design Bit
More informationCOMBINATIONAL LOGIC FUNCTIONS
COMBINATIONAL LOGIC FUNCTIONS Digital logic circuits can be classified as either combinational or sequential circuits. A combinational circuit is one where the output at any time depends only on the present
More informationUNIT II COMBINATIONAL CIRCUITS:
UNIT II COMBINATIONAL CIRCUITS: INTRODUCTION: The digital system consists of two types of circuits, namely (i) (ii) Combinational circuits Sequential circuits Combinational circuit consists of logic gates
More informationWe are here. Assembly Language. Processors Arithmetic Logic Units. Finite State Machines. Circuits Gates. Transistors
CSC258 Week 3 1 Logistics If you cannot login to MarkUs, email me your UTORID and name. Check lab marks on MarkUs, if it s recorded wrong, contact Larry within a week after the lab. Quiz 1 average: 86%
More informationSynchronous Sequential Logic
1 IT 201 DIGITAL SYSTEMS DESIGN MODULE4 NOTES Synchronous Sequential Logic Sequential Circuits - A sequential circuit consists of a combinational circuit and a feedback through the storage elements in
More informationUNIVERSITI TENAGA NASIONAL. College of Information Technology
UNIVERSITI TENAGA NASIONAL College of Information Technology BACHELOR OF COMPUTER SCIENCE (HONS.) FINAL EXAMINATION SEMESTER 2 2012/2013 DIGITAL SYSTEMS DESIGN (CSNB163) January 2013 Time allowed: 3 hours
More informationSIR C.R.REDDY COLLEGE OF ENGINEERING ELURU DIGITAL INTEGRATED CIRCUITS (DIC) LABORATORY MANUAL III / IV B.E. (ECE) : I - SEMESTER
SIR C.R.REDDY COLLEGE OF ENGINEERING ELURU 534 007 DIGITAL INTEGRATED CIRCUITS (DIC) LABORATORY MANUAL III / IV B.E. (ECE) : I - SEMESTER DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING DIGITAL
More informationSample Test Paper - I
Scheme G Sample Test Paper - I Course Name : Computer Engineering Group Marks : 25 Hours: 1 Hrs. Q.1) Attempt any THREE: 09 Marks a) Define i) Propagation delay ii) Fan-in iii) Fan-out b) Convert the following:
More informationNumber System. Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary
Number System Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary BOOLEAN ALGEBRA BOOLEAN LOGIC OPERATIONS Logical AND Logical OR Logical COMPLEMENTATION
More informationIT T35 Digital system desigm y - ii /s - iii
UNIT - II Combinational Logic Adders subtractors code converters binary parallel adder decimal adder magnitude comparator encoders decoders multiplexers demultiplexers-binarymultiplier Parity generator
More informationBoolean Algebra. Digital Logic Appendix A. Postulates, Identities in Boolean Algebra How can I manipulate expressions?
Digital Logic Appendix A Gates Combinatorial Circuits Sequential Circuits Other operations NAND A NAND B = NOT ( A ANDB) = AB NOR A NOR B = NOT ( A ORB) = A + B Truth tables What is the result of the operation
More informationUniversity of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering
University of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering Final Examination ECE 241F - Digital Systems Examiners: J. Rose and
More informationLogic. Combinational. inputs. outputs. the result. system can
Digital Electronics Combinational Logic Functions Digital logic circuits can be classified as either combinational or sequential circuits. A combinational circuit is one where the output at any time depends
More informationCombinational Logic. Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C.
Combinational Logic ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2010 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Combinational Circuits
More informationS.Y. Diploma : Sem. III [CO/CM/IF/CD/CW] Digital Techniques
S.Y. Diploma : Sem. III [CO/CM/IF/CD/CW] Digital Techniques Time: 3 Hrs.] Prelim Question Paper Solution [Marks : 100 Q.1(a) Attempt any SIX of the following : [12] Q.1(a) (i) Derive AND gate and OR gate
More informationLOGIC CIRCUITS. Basic Experiment and Design of Electronics
Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Outline Combinational logic circuits Output
More informationLOGIC CIRCUITS. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D.
Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Digital IC packages TTL (transistor-transistor
More informationNumber representation
Number representation A number can be represented in binary in many ways. The most common number types to be represented are: Integers, positive integers one-complement, two-complement, sign-magnitude
More informationDigital Logic Appendix A
Digital Logic Appendix A Boolean Algebra Gates Combinatorial Circuits Sequential Circuits 1 Boolean Algebra George Boole ideas 1854 Claude Shannon, apply to circuit design, 1938 Describe digital circuitry
More informationSequential vs. Combinational
Sequential Circuits Sequential vs. Combinational Combinational Logic: Output depends only on current input TV channel selector (-9) inputs system outputs Sequential Logic: Output depends not only on current
More informationSynchronous Sequential Circuit Design. Digital Computer Design
Synchronous Sequential Circuit Design Digital Computer Design Races and Instability Combinational logic has no cyclic paths and no races If inputs are applied to combinational logic, the outputs will always
More informationTime Allowed 3:00 hrs. April, pages
IGITAL ESIGN COEN 32 Prof. r. A. J. Al-Khalili Time Allowed 3: hrs. April, 998 2 pages Answer All uestions No materials are allowed uestion a) esign a half subtractor b) esign a full subtractor c) Using
More informationBoolean Algebra. Digital Logic Appendix A. Boolean Algebra Other operations. Boolean Algebra. Postulates, Identities in Boolean Algebra
Digital Logic Appendix A Gates Combinatorial Circuits Sequential Circuits George Boole ideas 1854 Claude Shannon, apply to circuit design, 1938 (piirisuunnittelu) Describe digital circuitry function programming
More informationIntroduction to Digital Logic Missouri S&T University CPE 2210 Subtractors
Introduction to Digital Logic Missouri S&T University CPE 2210 Egemen K. Çetinkaya Egemen K. Çetinkaya Department of Electrical & Computer Engineering Missouri University of Science and Technology cetinkayae@mst.edu
More informationChapter 5. Digital systems. 5.1 Boolean algebra Negation, conjunction and disjunction
Chapter 5 igital systems digital system is any machine that processes information encoded in the form of digits. Modern digital systems use binary digits, encoded as voltage levels. Two voltage levels,
More informationChapter 7 Logic Circuits
Chapter 7 Logic Circuits Goal. Advantages of digital technology compared to analog technology. 2. Terminology of Digital Circuits. 3. Convert Numbers between Decimal, Binary and Other forms. 5. Binary
More informationLecture 12: Adders, Sequential Circuits
Lecture 12: Adders, Sequential Circuits Today s topics: Carry-lookahead adder Clocks, latches, sequential circuits 1 Speed of Ripple Carry The carry propagates thru every 1-bit box: each 1-bit box sequentially
More informationELECTRONICS & COMMUNICATION ENGINEERING PROFESSIONAL ETHICS AND HUMAN VALUES
EC 216(R-15) Total No. of Questions :09] [Total No. of Pages : 02 II/IV B.Tech. DEGREE EXAMINATIONS, DECEMBER- 2016 First Semester ELECTRONICS & COMMUNICATION ENGINEERING PROFESSIONAL ETHICS AND HUMAN
More informationCprE 281: Digital Logic
CprE 281: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Fast Adders CprE 281: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev HW5
More informationECE 2300 Digital Logic & Computer Organization
ECE 23 Digital Logic & Computer Organization Spring 28 Combinational Building Blocks Lecture 5: Announcements Lab 2 prelab due tomorrow HW due Friday HW 2 to be posted on Thursday Lecture 4 to be replayed
More informationCMSC 313 Lecture 18 Midterm Exam returned Assign Homework 3 Circuits for Addition Digital Logic Components Programmable Logic Arrays
MS 33 Lecture 8 Midterm Exam returned Assign Homework 3 ircuits for Addition Digital Logic omponents Programmable Logic Arrays UMB, MS33, Richard hang MS 33, omputer Organization & Assembly
More informationCSE 140L Spring 2010 Lab 1 Assignment Due beginning of the class on 14 th April
CSE 140L Spring 2010 Lab 1 Assignment Due beginning of the class on 14 th April Objective - Get familiar with the Xilinx ISE webpack tool - Learn how to design basic combinational digital components -
More informationAppendix A: Digital Logic. Principles of Computer Architecture. Principles of Computer Architecture by M. Murdocca and V. Heuring
- Principles of Computer rchitecture Miles Murdocca and Vincent Heuring 999 M. Murdocca and V. Heuring -2 Chapter Contents. Introduction.2 Combinational Logic.3 Truth Tables.4 Logic Gates.5 Properties
More informationBinary addition (1-bit) P Q Y = P + Q Comments Carry = Carry = Carry = Carry = 1 P Q
Digital Arithmetic In Chapter 2, we have discussed number systems such as binary, hexadecimal, decimal, and octal. We have also discussed sign representation techniques, for example, sign-bit representation
More informationCombinational Logic. Mantıksal Tasarım BBM231. section instructor: Ufuk Çelikcan
Combinational Logic Mantıksal Tasarım BBM23 section instructor: Ufuk Çelikcan Classification. Combinational no memory outputs depends on only the present inputs expressed by Boolean functions 2. Sequential
More informationChapter 3. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 3 <1>
Chapter 3 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 3 Chapter 3 :: Topics Introduction Latches and Flip-Flops Synchronous Logic Design Finite
More informationOverview. Arithmetic circuits. Binary half adder. Binary full adder. Last lecture PLDs ROMs Tristates Design examples
Overview rithmetic circuits Last lecture PLDs ROMs Tristates Design examples Today dders Ripple-carry Carry-lookahead Carry-select The conclusion of combinational logic!!! General-purpose building blocks
More informationDigital Logic (2) Boolean Algebra
Digital Logic (2) Boolean Algebra Boolean algebra is the mathematics of digital systems. It was developed in 1850 s by George Boole. We will use Boolean algebra to minimize logic expressions. Karnaugh
More informationIntroduction EE 224: INTRODUCTION TO DIGITAL CIRCUITS & COMPUTER DESIGN. Lecture 6: Sequential Logic 3 Registers & Counters 5/9/2010
EE 224: INTROUCTION TO IGITAL CIRCUITS & COMPUTER ESIGN Lecture 6: Sequential Logic 3 Registers & Counters 05/10/2010 Avinash Kodi, kodi@ohio.edu Introduction 2 A Flip-Flop stores one bit of information
More informationCPS 104 Computer Organization and Programming Lecture 11: Gates, Buses, Latches. Robert Wagner
CPS 4 Computer Organization and Programming Lecture : Gates, Buses, Latches. Robert Wagner CPS4 GBL. RW Fall 2 Overview of Today s Lecture: The MIPS ALU Shifter The Tristate driver Bus Interconnections
More informationCSE 140 Spring 2017: Final Solutions (Total 50 Points)
CSE 140 Spring 2017: Final Solutions (Total 50 Points) 1. (Boolean Algebra) Prove the following Boolean theorem using Boolean laws only, i.e. no theorem is allowed for the proof. State the name of the
More informationChapter 2 Basic Arithmetic Circuits
Chapter 2 Basic Arithmetic Circuits This chapter is devoted to the description of simple circuits for the implementation of some of the arithmetic operations presented in Chap. 1. Specifically, the design
More informationLecture 13: Sequential Circuits
Lecture 13: Sequential Circuits Today s topics: Carry-lookahead adder Clocks and sequential circuits Finite state machines Reminder: Assignment 5 due on Thursday 10/12, mid-term exam Tuesday 10/24 1 Speed
More informationLecture 3 Review on Digital Logic (Part 2)
Lecture 3 Review on Digital Logic (Part 2) Xuan Silvia Zhang Washington University in St. Louis http://classes.engineering.wustl.edu/ese461/ ircuit Optimization Simplest implementation ost criterion literal
More informationSchedule. ECEN 301 Discussion #25 Final Review 1. Date Day Class No. 1 Dec Mon 25 Final Review. Title Chapters HW Due date. Lab Due date.
Schedule Date Day Class No. Dec Mon 25 Final Review 2 Dec Tue 3 Dec Wed 26 Final Review Title Chapters HW Due date Lab Due date LAB 8 Exam 4 Dec Thu 5 Dec Fri Recitation HW 6 Dec Sat 7 Dec Sun 8 Dec Mon
More informationShow that the dual of the exclusive-or is equal to its compliment. 7
Darshan Institute of ngineering and Technology, Rajkot, Subject: Digital lectronics (2300) GTU Question ank Unit Group Questions Do as directed : I. Given that (6)0 = (00)x, find the value of x. II. dd
More information1 Short adders. t total_ripple8 = t first + 6*t middle + t last = 4t p + 6*2t p + 2t p = 18t p
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Study Homework: Arithmetic NTU IC54CA (Fall 2004) SOLUTIONS Short adders A The delay of the ripple
More informationUNSIGNED BINARY NUMBERS DIGITAL ELECTRONICS SYSTEM DESIGN WHAT ABOUT NEGATIVE NUMBERS? BINARY ADDITION 11/9/2018
DIGITAL ELECTRONICS SYSTEM DESIGN LL 2018 PROFS. IRIS BAHAR & ROD BERESFORD NOVEMBER 9, 2018 LECTURE 19: BINARY ADDITION, UNSIGNED BINARY NUMBERS For the binary number b n-1 b n-2 b 1 b 0. b -1 b -2 b
More informationDigital Electronics Circuits 2017
JSS SCIENCE AND TECHNOLOGY UNIVERSITY Digital Electronics Circuits (EC37L) Lab in-charge: Dr. Shankraiah Course outcomes: After the completion of laboratory the student will be able to, 1. Simplify, design
More informationFundamentals of Computer Systems
Fundamentals of Computer Systems Review for the Final Stephen A. Edwards Columbia University Summer 25 The Final 2 hours 8 problems Closed book Simple calculators are OK, but unnecessary One double-sided
More informationCPE100: Digital Logic Design I
Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu CPE100: Digital Logic Design I Midterm02 Review http://www.ee.unlv.edu/~b1morris/cpe100/ 2 Logistics Thursday Nov. 16 th In normal lecture (13:00-14:15)
More informationCs302 Quiz for MID TERM Exam Solved
Question # 1 of 10 ( Start time: 01:30:33 PM ) Total Marks: 1 Caveman used a number system that has distinct shapes: 4 5 6 7 Question # 2 of 10 ( Start time: 01:31:25 PM ) Total Marks: 1 TTL based devices
More informationCombinational Logic Design Combinational Functions and Circuits
Combinational Logic Design Combinational Functions and Circuits Overview Combinational Circuits Design Procedure Generic Example Example with don t cares: BCD-to-SevenSegment converter Binary Decoders
More informationComputers also need devices capable of Storing data and information Performing mathematical operations on such data
Sequential Machines Introduction Logic devices examined so far Combinational Output function of input only Output valid as long as input true Change input change output Computers also need devices capable
More informationSection 3: Combinational Logic Design. Department of Electrical Engineering, University of Waterloo. Combinational Logic
Section 3: Combinational Logic Design Major Topics Design Procedure Multilevel circuits Design with XOR gates Adders and Subtractors Binary parallel adder Decoders Encoders Multiplexers Programmed Logic
More informationMAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified)
WINTER 17 EXAMINATION Subject Name: Digital Techniques Model Answer Subject Code: 17333 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given
More informationon candidate s understanding. 7) For programming language papers, credit may be given to any other program based on equivalent concept.
WINTER 17 EXAMINATION Subject Name: Digital Techniques Model Answer Subject Code: 17333 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given
More informationWORKBOOK. Try Yourself Questions. Electrical Engineering Digital Electronics. Detailed Explanations of
27 WORKBOOK Detailed Eplanations of Try Yourself Questions Electrical Engineering Digital Electronics Number Systems and Codes T : Solution Converting into decimal number system 2 + 3 + 5 + 8 2 + 4 8 +
More informationClass Website:
ECE 20B, Winter 2003 Introduction to Electrical Engineering, II LECTURE NOTES #5 Instructor: Andrew B. Kahng (lecture) Email: abk@ece.ucsd.edu Telephone: 858-822-4884 office, 858-353-0550 cell Office:
More information