S.Y. Diploma : Sem. III [CO/CM/IF/CD/CW] Digital Techniques s complement 2 s complement 1 s complement

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1 S.Y. Diploma : Sem. III [CO/CM/IF/CD/CW] Digital Techniques Time: 3 Hrs.] Prelim Question Paper Solution [Marks : Q.(a) (i) () (2) s COMPLEMENT s COMPLEMENT 2s COMPLEMENT 2s COMPLEMENT + Q.(a) (ii) () (2) 2 = (2) H + Hk 6 9 = (69) H Q.(a) (iii) s complement 2 s complement s complement Q.(a) (iv) Logic Symbol and Truth table for 2i/p la NAND gate Truth Table A y A y Symbol Q.(a) (v) i) Commutative Laws : The laws of commutation allow us to arrange variables in any order without changing the result. With two variables A and, these are given by A + = + A A = A ii) Associative Laws : Associative laws define the order in which the operations are performed. In both the OR and the AND operations, the grouping does not affect the result. This gives identities such as For the OR operation : (A + ) + C = A + ( + C). For the AND operation : (A ) C = A ( C) iii) Distributive Laws : The distribution of AND and OR operations is governed by the following laws. It is important to remember the rule of

2 : S.Y. Diploma DT precedence that, within a grouping, the AND operation always precedes the OR. The two important distributive laws are given by A ( + C) = (A ) + (A C) A + ( C) = (A + ) (A + C) Q.(a) (vi) Theorem : A = A The NOR operation is equivalent to ANDing the complements of the inputs. Theorem 2 : (A ) A The NAND operation is equivalent to ORing the complements ments of the inputs. Q.(a) (vii) Full subtractor symbol and truth table A Truth table for a full subtractor Inputs Outputs A in (A n in ) (minuend) (Subtrahend) Previous Difference orrow borrow Q.(a) (viii) Flip flop can be considered as a basic memory cell because it stores the value on the data line with the advantage of the output being synchronized to a clock. Example : in Diff orrow an 2

Prelim Question Paper Solution The clocked RS flip-flop shown above.

clock input. It is also called as level el triggered SR-FF.

response to any change made at the input.

For this circuit, the change in output will take place if and only

In short, this circuit will operate as an SR flipflop if clock = but

3 Prelim Question Paper Solution The clocked RS flip-flop shown above. It is basically the S - R flip-flop using NAND gates with an ad clock input. It is also called as level el triggered SR-FF. The outputs of simple RS flip-flop used to change instantly in response to any change made at the input. ut this doesn t happen pen with the clocked S R flip-flop. For this circuit, the change in output will take place if and only if the clock input is made active i.e Clk=. In short, this circuit will operate as an SR flipflop if clock = but there is no change in the outputs if clock =. Q.(b) (i) Draw pin configuration n of TTL IC s used for AND gate and NAND gate. 748(AND) Pin Diagram: 3

: S.Y. Diploma DT 74(NAND): Pin Diagram: Q.

4 : S.Y. Diploma DT 74(NAND): Pin Diagram: Q.(b) (ii) D D 2 : MUX S D out S S S S 2 Q.(b) (iii) Half Adders Half adder is a combinational logic circuit with two inputs and two outputs. It is the basic building block for addition of two single bit numbers. This circuit has two outputs carry and sum. D out D D D D 7 8 : MUX D 7 nk an D out 4

5 Prelim Question Paper Solution Q.2(a) (i) Propagation delay (or speed of operation) 5 % Input Output t PHL 5 % The delay times are measured between the 5 % voltage levels of input and output waveforms. There are two delay times t PHL when output goes from High to Low t PLH when output goes from Low to High Propagation delay is average of above two delay times. (ii) Power Dissipation Power dissipation in ICs is the process in which IC consumes electrical energy and dissipate this energy both by the action of switching devices and by energy lost in the form of heat due to impedance of electronic circuits. (iii) Noise immunity (or Noise margin) The input & output voltage levels defined above are shown in figure. Stray electric and magnetic fields state noise may induce unwanted voltages, margin known as noise, on the connecting wires between logic circuits. This may cause the voltage at the input to a logic state noise circuit cuit to drop below V H or rise margin above V L and may produce undesired operation. The circuit s ability to tolerate noise signals is referred to as the noise immunity, a quantitative measure of which is called noise margin. There are two types of noise margins. (a) High level noise margin (NM H ) NM H = V H V H (b) Low level noise margin (NM L ) NM L = V L V L (iv) Fan in The total number of inputs connected to the gate is called as fan in of the gate. Y AC fan in = 3 t PLH V H V H V L V L Voltages V H V H V L V L 5

6 : S.Y. Diploma DT Q.2(b) (i) using s complement method. s complement + + (ii) using 2 s complement method. s complement + 2 s complement Q.2(c) Prove that : YZ WXZ WXYZ WYZ Z LHS = YZ WXZ(Y Y) WXYZ WYZ = YZ WXYZ WXYZ WXYZ WYZ = YZ WYZ(X X) WXYZ WYZ = YZ WYZ WXYZ WYZ = YZ( WX) WYZ WYZ = YZ WYZ WYZ = YZ (W W)YZ = YZ YZ = (Y Y)Z = Z Vi dy =dy ya ala laa Q.2(d) K-map for Y = M dm (, 3, 5, 7, 9,, 3, 5) A CD V V =idz Logical Diagram : From K-map we get Y = D D Y = D 6

constructed by using unipolar (MOSFET) components only. ii) Packing density is less hence less data can be accommodated.

The data is stored in the inherent capacitor of MOSFETS.

v) Transmission gates are not used. Transmission gates are used in the circuit, which can conduct in both the direction. vi) More costly Less costly Q.

Some of the most important ECL characteristics are as follows : i) Maximum propagation delay : for the latest ECL gates the propagation delay is very

iv) Worst case noise margin is only 5 mv. So ECL device are unreliable to work in noisy environments.

7 Prelim Question Paper Solution Q.2(e) Comparison between Static RAM and Dynamic RAM Static RAM Dynamic RAM i) Can be constructed by using either unipolar or bipolar components Can be constructed by using unipolar (MOSFET) components only. ii) Packing density is less hence less data can be accommodated. Packing density is very large & hence large data can be accommodated. iii) asic element of storing the data if F/F. The data is stored in the inherent capacitor of MOSFETS. iv) Data stored permanent can be Refreshing of the stored data after allowed & no refreshing operation is every few milli sec. is essential. necessary. v) Transmission gates are not used. Transmission gates are used in the circuit, which can conduct in both the direction. vi) More costly Less costly Q.2(f) Diagram of binary weighted DAC and its working inary weighted resistors (Reference voltage) Q.3(a) Characteristics acteristics of ECL logic families. Some of the most important ECL characteristics are as follows : i) Maximum propagation delay : for the latest ECL gates the propagation delay is very short, of the order of 5 ps. ii) Average power dissipation : 5 mw (for advanced ECL gates) iii) Speed-power product (SPP) :.5pJ. iv) Worst case noise margin is only 5 mv. So ECL device are unreliable to work in noisy environments. v) ECL devices generally produce an output an its complement (e.g. OR/NOR). So additional inverter is necessary. vi) Due to emitter follower stages, the output impedance is very low. vii) Due to low output impedance, the fan out is typically equal to 25. viii) Typical power dissipation for the standard ECL gate is 25 mw which is somewhat higher than that of 74 AS series. ix) The current flowing in ECL circuits remains almost constant so no current transients are observed and so associated noise also is less. Vidy nkar arr 7

3(c) Symbol, logical equation and truth table of 3 i/p AND gate and 3 i/p OR gate

3(d) Arithmetic Logic Unit (ALU) ALU is a very widely used and popular

It is capable of performing the arithmetic as well as the logic operations.

748 is a 24-pin IC in dual in line (DIP) package.

It can perform a total of 6 arithmetic operations which includes addition,

8 : S.Y. Diploma DT Q.3(b) (i) + (ii) + D C = (6) + 7 = (7) ( 3) = (9) + = (9) ( 8) Q.3(c) Symbol, logical equation and truth table of 3 i/p AND gate and 3 i/p OR gate A y A y C C y = A.. C y = A + + C Q.3(d) Arithmetic Logic Unit (ALU) ALU is a very widely used and popular combinational circuit. It is capable of performing the arithmetic as well as the logic operations. ALU is the heart of any microprocessor. sor. 748 is a 24-pin IC in dual in line (DIP) package.a (A-A3 and (-3) are the two 4 bit variables. It can perform a total of 6 arithmetic operations which includes addition, subtraction, compare and double operations. It provides many logic operations such as AND, OR, NOR, NAND, EX-OR, compare, etc. on the two four bit variables. an 748 is a high speed 4 bit parallel ALU. It is controlled by four function select inputs (S-S3). These lines can select 6 different operations for one mode (arithmetic) and 6 another operations for the other mode (logic). M is 8

9 Prelim Question Paper Solution the mode control input. It decides the mode of operation to be either arithmetic or logic. Mode M =. For arithmetic operations. M = For logic operations. G and P outputs are used when a number of 748 circuits are to be used in cascade alongwith 7482 the look ahead carry generator circuit to make the arithmetic operations faster. ar Function Table for IC 748with active high data and C n = 9

10 : S.Y. Diploma DT Q.3(e) I/P D Q A R Q J Q C Q A S Q K Q C LED Case : LED ON Q = Q C = J = Q = R = D = C Case 2: LED OFF Q = Q C = J = Q = R = D = VR Q.3(f) =.2 V = 8 = V R =.6 V C ar i) 4.VR = 8 ii) 5VR = 8 VR = =.8V 2 = 5.6 = V 8 Q.4(a) The dual of AND is OR and the dual of OR is AND. According to the duality theorem the following conversions are possible in a given oolean expression. i) Change each AND operation to an OR operation. ii) Change each OR operation to an AND operation. iii) Complement any or appearing in the expression. Duality theorem is sometimes useful in creating new expressions from the given oolean expressions. Q.4(b) Universal Gate NAND and NOR are referred to as Universal Logic Gates since all the basic logic gates can be constructed using either the NAND or NOR logic gates only.

11 Prelim Question Paper Solution Q.4(c) : 4 demux using NAND gate k Function Table Input Output al l D IN S S Y Y Y 2 Y 3 E E E E E E E E Q.4(d) Table (SN54/74LS48)

12 : S.Y. Diploma DT ) I / RO is wired-and logic, serving as blacking input (I) and/or rippleblacking output (RO). The blacking out (I) must be open or held at a HIGH level when output functions through 5 are desired, and rippleblacking input (RI) must be open or at a HIGH level if blacking of a decimal is not desired. X-input may be HIGH or LOW. 2) When a LOW level is applied to the blacking input (forced condition) all segment outputs go to a LOW level, regardless of the state of any other input condition. 3) When ripple-blacking input (RI) and inputs A,, C and D are at LOW level, with the lamp test input at HIGH level, all segment outputs ts go to a HIGH level and the ripple-blacking output (RO) given to a LOW level (response condition). 4) When the blacking input/ripple-blacking output (I / RO) is open or held at a HIGH level, and a LOW level is applied to lamp-test input, all segment outputs go to a LOW level. Q.4(e) 8: multiplexer using basic gates D 4 D 5 D 6 D 7 2

13 Prelim Question Paper Solution Q.4(f) (i) 5 Require 4 bits (in 2s complement) 4 F/F required (ii) 83 Require 7 bits 7 F/Fs required (iii) 99 Require 7 bits 7 F/Fs required (iv) Require 4 bits 4 F/F required Q.5(a) y = (A + ) (A + C) = A.A + A.C +.A +.C = A + A.C +.A +.C C = A ( + C) + A + C = A ( + ) + C = A + C +ya Q.5(b) (i) y = A + AC + A + AC = A ( + C) + A + AC ḋy = A + A AC = (A + A ) + AC = + AC (ii) y = (A + ) (A + ) A = A. A = (A + ) A + = A A = A. A + A = + A = A A VV =dy )ya an Q.5(c) Table A Carry Sum y S S V D = D = D = D 2 = y 3

: S.Y. Diploma DT Q.5(d) Truth table of the full adder A Sum C C in A Sum Carry out Q.5(e) Figure (a) show the block diagram of 748. There are 8 parity inputs A to H and two cascading cading inputs.

14 : S.Y. Diploma DT Q.5(d) Truth table of the full adder A Sum C C in A Sum Carry out Q.5(e) Figure (a) show the block diagram of 748. There are 8 parity inputs A to H and two cascading cading inputs. There are two outputs even and odd. And there are two cascading inputs named EVEN and ODD. The pin configuration of IC 748 is shown Figure (b). C out Fig. (a) : lock diagram of 748. Fig. (b) : Pin configuration of 748. k MUX MUX MUX 2 an S C out 4

15 Prelim Question Paper Solution Functional table for 748 : Parity of inputs Cascading inputs Row no. Outputs (A to H) EVEN ODD Even Odd Even 2 Odd 3 Even 4 Odd 5 X 6 X Q.5(f) 3-bit synchronous counter Excitation equation of D Flip-flop. Q n Q n * D Previous State Next State Excitation equation Count Q 2 Q Q Q 2 * Q * Q * D 2 D D nexci for D 2 for D Q Q Q Q Q 2 D 2 = QQQ 2 QQ 2 QQ 2 D = QQ QQ = Q Q for D Q 2 Q Q Q 2 an a 5

16 : S.Y. Diploma DT D 2 = Q Cl Q Q Q.6(a) (i) Theorem : (A ) A LHS RHS A A + A A A. Theorem 2 : (A ) A D Q Q RHS A A aa A A. alhs Q.6(a) (ii) (A + C) (A + D) ( + C) ( + D) = [A + (C. D)] [ + (C. D)] Distributive = (C. D) + (A. ) Distributive = A + CD Commutative D Q 2 Q 2 Q.6(b) (i) Purpose of encoder and decoder Decoders will have N inputs, and 2 N output. Let's say that we have two inputs (A and ), and 4 outputs (M N O P). Decoders will satisfy the following truth table: A M N O P D ana ank ann ar 6

Q.6(b) (ii) Encoders Prelim Question Paper Solution inary numbers come in, and essentially select which wire to send a signal on.

When a bit comes in on an input wire, the encoder outputs the physical address of that wire.

Encoders are used to convert decimal numbers to equivalent binary numbers. An encoder has n number of input lines and m number of output lines.

If we have 2 outputs we can accommodate modate 4 input 3 outputs we can accommodate odate 8 input n outputs we can accommodate 2 n input lines.

6(c) 3-bit R 2R ladder DAC 'm' output lines The basic theory of the R-2R ladder network is that current flowing through any input resistor (2R) encounters two

17 Q.6(b) (ii) Encoders Prelim Question Paper Solution inary numbers come in, and essentially select which wire to send a signal on. Encoders work in exactly the opposite way as decoders, taking 2 N inputs, and having N outputs. When a bit comes in on an input wire, the encoder outputs the physical address of that wire. It takes 2^n inputs and gives out n outputs, the enable pin should be kept for enabling the circuit. Encoders are used to convert decimal numbers to equivalent binary numbers. An encoder has n number of input lines and m number of output lines. An encoder produces a m bit binary code corresponding to the digital input number. If we have 2 outputs we can accommodate modate 4 input 3 outputs we can accommodate odate 8 input n outputs we can accommodate 2 n input lines. The encoder accepts an n input digital word and converts it into a m bit another digital word. Q.6(c) 3-bit R 2R ladder DAC 'm' output lines The basic theory of the R-2R ladder network is that current flowing through any input resistor (2R) encounters two possible paths at the far end. The effective resistances of both paths are the same (also 2R), so the incoming current splits equally along both paths. The half-current that flows back towards lower orders of magnitude does not reach the op amp, and therefore has no effect on the output voltage. The half that takes the path towards the op amp along the ladder can affect the output. The inverting input of the op-amp is at virtual earth. Current flowing in the elements of the ladder network is therefore unaffected by switch positions. 7

18 : S.Y. Diploma DT If we label the bits (or inputs) bit to bit N the output voltage caused by connecting a particular bit to V r with all other bits grounded is: Vr V out = 2N Vr where N is the bit number. For bit, V out = 2, for bit 2, V Vr out = 4 etc. Since an R/2R ladder is a linear circuit, we can apply the principle ple of superposition to calculate V out. The expected output voltage is calculated by summing the effect of all bits connected to V r. For example, if bits and 3 are connected to V r with all other inputs grounded, the output voltage is calculated by: Vr Vr V out = 2 8 5Vr which reduces to V out = 8. 8

S.Y. Diploma : Sem. III [CO/CM/IF/CD/CW] Digital Techniques

S.Y. Diploma : Sem. III [CO/CM/IF/CD/CW] Digital Techniques Time: 3 Hrs.] Prelim Question Paper Solution [Marks : 100 Q.1(a) Attempt any SIX of the following : [12] Q.1(a) (i) Derive AND gate and OR gate