Chapter 5 Arithmetic Circuits

Transcription

1 Chapter 5 Arithmetic Circuits SKEE2263 Digital Systems Mun im/ismahani/izam {munim@utm.my,e-izam@utm.my,ismahani@fke.utm.my} February 11, 2016

2 Table of Contents 1 Iterative Designs 2 Adders 3 High-Speed Adders 4 Subtractors 5 Condition Codes 6 Multipliers 7 High-Speed Multipliers

3 Iterative Designs a 7-0 b 7-0 z Logic circuit y 7-0 c A circuit can be decomposed into smaller 'bit slice' blocks to facilitate the design process. a 7 b 7 a 1 b 1 a 0 b 0 z c y 7 y 1 y 0

4 Half Adder a b c s s = a b c = ab a b s c

5 Full Adder Boolean Expressions a i b i c i c i+1 s i s i = a i b i c i c i+1 = a i b i + a i c i + b i c i

6 Full Adder Two-Level Realization a i b i s i c i c i+1

7 Full Adder Multi-Level, Hierarchical Realization a i Half adder Half adder b i s i c i+1 c i s i = (a i b i ) c i = a i b i c i c i+1 = a i b i + (a i b i )c i = a i b i + (a i + b i )c i = a i b i + a i c i + b i c i

8 Full Adder Schematic for Cascadable Module ai bi a b i i ci+1 FA c c i+1 c i si s i

9 4-bit Ripple Adder a b a b a b a b c 4 FA FA FA FA c c c c s 3 2 s s s 1 0

10 Delay Analysis of Cascadable Full Adder a b c in 2t 2τ s τ τ τ c out

11 Delay Analysis of 4-bit Adder a 3 b3 a 2 b 2 a 1 b 1 a 0 b 0 c 4 8τ 6τ 4τ 2τ c 0 c 3 c 2 c 1 10τ s 3 s 2 s 1 s 0 Delay expression in terms of τ: t p = [4 + 2(n 2) + 2]τ = [2n + 2]τ In O -notation, delay is linear with number of bits O(n) Generic delay expression: t p = (n 1)t carry + t sum

12 Carry Lookahead Adder Analysis of Carry Behavior a i b i c i c i+1 Decision g i p i Carry kill Carry 0 1 c i propagate Carry generate 1 1 c i+1 = 1 : when a i = b i = 1 (regardless of the carry in) or, when a i b i and the carry-in (from the previous stage) is 1

13 Carry Lookahead Adder Derivation of p i, g i Carry generate (g i ): a signal that is true when a i b i = 1. g i = a i b i Carry propagate (p i ): propagates the carry-in (c i ) to a stage to the next stage (i.e., c i+1 c i ) if the half sum a i b i = 1. p i = a i + b i

14 Carry Lookahead Adder ai bi ai bi a i p g b i c i s i p i 0 g i c i+1 1 c i Partial Full Adder (PFA) p i, g i w.r.t. carries

15 Carry Lookahead Adder Carry-out Equations c 1 = g 0 + p 0 c 0 c 2 = g 1 + p 1 c 1 = g 1 + p 1 (g 0 + p 0 c 0 ) = g 1 + p 1 g 0 + p 1 p 0 c 0 c 3 = g 2 + p 2 c 2 = g 2 + p 2 (g 1 + p 1 g 0 + p 1 p 0 c 0 ) = g 2 + p 2 g 1 + p 2 p 1 g 0 + p 2 p 1 p 0 c 0 c 4 = g 3 + p 3 c 3 = g 3 + p 3 (g 2 + p 2 g 1 + p 2 p 1 g 0 + p 2 p 1 p 0 c 0 ) = g 3 + p 3 g 2 + p 3 p 2 g 1 + p 3 p 2 p 1 g 0 + p 3 p 2 p 1 p 0 c 0

16 Carry Lookahead Adder Carry Lookahead Generator (CLG) p 3 g 3 p 2 g 2 p 1 g 1 p 0 g 0 c 0 c 4 c 3 c 2 c 1

17 Carry Lookahead Adder 4-bit Carry Lookahead Adder a3 b3 a2 b2 a1 b1 a0 b0 PFA PFA PFA PFA c0 c s3 s s s g 3 p 3 c g 3 2 p 2 c g p c g p c 4 Carry Lookahead Generator Maximum gate delay for the carry generation is 3 τ. The full adders introduce two more gate delays. the worst case path is 5 τ.

18 Carry Lookahead Adder 12-bit Carry Lookahead Adder a 11-8 b 11-8 a 7-4 b 7-4 a 3-0 b c 12 4-bit carry lookahead adder c 8 4-bit carry lookahead adder c 4 4-bit carry lookahead adder c 0 4 s 11-8 s 7-4 s 3-0 Total delay = 5 τ

19 Carry Lookahead Adder 16-bit Carry Lookahead Adder b a b 11-8 b 7-4 b 3-0 a 11-8 a 7-4 a t CLA c 12 CLA c 8 CLA c 4 CLA c 0 4 s s 11-8 s 7-4 s 3-0 P 3 G 3 P 2 G 2 P 1 G 1 P 0 G 0 c 16 Group Carry Lookahead Logic Total delay = 10 τ.

20 Carry Select Adder a 7-4 b c 4 c 8,0 4-bit adder 0 a 7-4 b c 8,1 4-bit adder a 3-0 b c 4 4-bit adder c c 8 s 7-4 s 3-0 Total delay = delay of 1 4-bit adder + 2 τ.

21 Carry Save Adder 3:2 Compression Costing Just 2τ A B C n n n CSA n+1 n+1 Y X (Carry vector) (Bitwise sum) A B C S C

22 Carry Save Adder Adding 3 numbers using Ripple Carry Adders only a 2 b 2 a 3 b 3 a 1 b 1 a 0 b 0 RCA FA FA FA HA CPA c 3 c 2 c c 1 0 HA FA FA FA HA s 5 s 4 s 3 s 2 s 1 s 0 Delay 30τ

23 Carry Save Adder Adding 3 numbers using Carry Save Adders a 2 b 2 a 3 b 3 c 3 a 1 b 1 c a 0 b 1 0 c 0 c 2 CSA FA FA FA FA CPA HA FA FA HA s 5 s 4 s 3 s 2 s 1 s 0 Delay 14τ

24 Adder Delay Summary Source:

25 Half Subtractor Input Output a b r (borrow) d (difference) d = a b + ab = a b r = a b a b d r

26 Full Subtractor Input Output a b r in r out d d = a b c + a bc + ab c + abc = a b c c out = a b c + a bc + a bc + abc = a c + a b + bc

27 Full Subtractor a i Half subtractor Half subtractor b i d i r i+1 r i

28 Ripple Subtractor a b a b a b a b e 4 FS FS FS FS e e e e d 3 2 d d d 1 0

29 Subtraction by Adding B n S = A + B + 1 = A + B Borrow c n A X n Y n-bit adder 1 n A - B Difference n c 0 B* where: = A + (2 n B) = A B + 2 n = A B B: Ones complement of B B : Two s complement of B

30 Adder/Subtractor a b a b a b a b Sub c 4 FA FA FA FA c c c c s 3 2 s s s 1 0

31 Flags Code Name Significance Z Zero Result is zero N Negative Result is < 0 C Carry The most significant bit produced a carry V Overflow Result has too many bits to be represented correctly

32 Z Flag True when all the bits in an n-bit result are 0s. Z = s n 1s n 2 s 1s 0 = (s n 1 + s n s 1 + s 0 )

33 N Flag The negative flag (N) is simply the sign bit. When it is high, the result was less than zero. N = s n 1

34 C Flag The carry out from the adder C = c n

35 V Flag True when a calculation produces a result that is greater than a register can store Method 1: a n 1 b n 1 s n 1 c n 1 c n 2 V V = a n 1 b n 1 s n 1 + a n 1b n 1s n 1 Method 2: V = c n c n 1

36 Flags Circuit a 3 b 3 a 2 b 2 a 1 b 1 a 0 b 0 Sub s 0 s 1 s 2 Z c in s 3 c 3 c 4 N C V c4 c c c1 c FA FA FA FA C V s 3 2 s s s 1 0

37 Deriving Other Relations Math Flags Flags Description Symbol (Unsigned) (Signed) = Equal Z Not equal Z < Less than C N V Less than or equal C + Z Z + (N V) Greater than or equal C N V > Greater than C Z Z (N V)

38 Binary Multiplication (13) 10 (11) 10 Partial Products (143) 10 Multiplicand M Multiplier Q Product P Multiplication is all about: 1 Generating the partial products 2 Adding the partial products

39 2 2 Multiplication a 1 a 0 b 0 a 1 a 0 b 1 b 1 b 0 a 1 b 0 a 0 b 0 a 1 b 1 a 0 b 1 p 3 p 2 p 1 p 0 HA a 1 HA a 0 p 3 p 2 p 1 p 0

40 Ripple Carry Array Multiplier a 3b0 a 2b0 a 1b0 a 3b1 a 2b1 a 1b1 a 0b1 a 0b0 p 0 HA FA FA HA a 3b2 a 2b2 a 1b2 a 0b2 p 1 FA FA FA HA a 3b3 a 2b3 a 1b3 a 0b3 p 2 FA FA FA HA p 7 p 6 p 5 p 4 p 3

41 M N Array Multiplier Critical Path Source:

42 Carry Save Adder Multiplier a 3b0 a 2b0 a 1b0 a 3b1 a 2b1 a 1b1 a 0b1 a 0b0 p 0 HA HA HA a 3b2 a 2b2 a 1b2 a 0b2 p 1 FA FA FA a 3b3 a 2b3 a 1b3 a 0b3 p 2 FA FA FA p 3 FA FA HA p 7 p 6 p 5 p 4

43 Carry Save Adder Multiplier Critical Path Source:

44 Wallace Tree Multiplier An application of carry save adder Source: