Lecture 8: Sequential Multipliers

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1 Lecture 8: Sequential Multipliers ECE 645 Computer Arithmetic 3/25/08 ECE 645 Computer Arithmetic Lecture Roadmap Sequential Multipliers Unsigned Signed Radix-2 Booth Recoding High-Radix Multiplication Principles Radix-4 Radix-4 Booth Recoding High-Radix Sequential Multipliers Using Carry-Save Adders Serial Multipliers Modular Multiplication 2

2 Required Reading B. Parhami, Computer Arithmetic: Algorithms and Hardware Design Chapter 9, Tree and Array Multipliers Chapter 10, High-Radix Multipliers Chapter 12, Variations in Multipliers Note errata at: 3 Sequential Multipliers ECE 645 Computer Arithmetic

3 Multiplication Architectures Area SEQUENTIAL MULTIPLIERS 5 Notation a Multiplicand a k a k-2... a 1 a 0 x Multiplier x k x k-2... x 1 x 0 p Product (a x) p 2k p 2k-2... p 2 p 1 p 0 If multiplicand and multiplier different sizes, usually multiplier is the smaller size 6

4 Multiplication of Two 4-bit Unsigned Binary Numbers in Dot Notation Partial Product 0 Partial Product 1 Partial Product 2 Partial Product 3 Number of partial products = number of bits in multiplier x Bit-width of each partial product = bit-width of multiplicand a 7 Basic Multiplication Equations p = a x k x = x i 2 i i=0 k p = a x = a x i 2 i = i=0 = x 0 a2 0 + x 1 a2 1 + x 2 a x k a2 k 8

5 Sequential Shift-and-Add Multipliers: Right-Shift Algorithm (Unsigned) p = a x = x 0 a2 0 + x 1 a2 1 + x 2 a x k a2 k = = (...((0 + x 0 a2 k )/2 + x 1 a2 k )/ x k a2 k )/2 = p (0) = 0 k times p (j+1) = (p (j) + x j a 2 k ) / 2 j=0..k p = p (k) 9 Sequential Shift-and-Add Multipliers: Right-Shift Algorithm 10

6 Right-shift multiplication algorithm: Example 11 Area Optimization for the Sequential Shift-and-Add Multiplier with the Right-shift Algorithm 12

7 Sequential Shift-and-Add Multipliers: Left-Shift Algorithm (Unsigned) p = a x = x 0 a2 0 + x 1 a2 1 + x 2 a x k a2 k = = (...((0 2 + x k a) 2 + x k-2 a) x 1 a) 2 + x 0 a= p (0) = 0 k times p (j+1) = (p (j) 2 + x k-j a) j=0..k p = p (k) 13 Sequential Shift-and-Add Multipliers: Left-Shift Algorithm More hardware than right-shift so right-shift is preferred 14

8 Left-shift multiplication algorithm: Example 15 Sequential Shift-and-Add Multipliers: Right-Shift Algorithm for Multiply-Add p (0) = y2 k p (j+1) = (p (j) + x j a 2 k ) / 2 j=0..k p = p (k) = (...((y2 k + x 0 a2 k )/2 + x 1 a2 k )/ x k a2 k )/2 = k times = y + x 0 a2 0 + x 1 a2 1 + x 2 a x k a2 k = y + a x 16

9 Sequential Shift-and-Add Multipliers: Left-Shift Algorithm for Multiply-Add p (0) = y2 -k p (j+1) = (p (j) 2 + x k-(j+1) a) j=0..k p = p (k) = (...((y2 -k 2 + x k a) 2 + x k-2 a) x 1 a) 2 + x 0 a = k times = y + x k a2 k + x k-2 a2 k x 1 a2 1 + x 0 a = y + a x 17 Signed Multiplication Previous sequential multipliers are for unsigned multiplication For signed multiplication: Right-shift sequential algorithms (shift-add) will work directly if 2's complement multiplier is POSITIVE Also assume sign-extended operation for p (i) + x i a If 2's complement multiplier is NEGATIVE than must use "negative weight" representation and subtract x k a instead of add in last cycle Also assume sign-extended operation for p (i) + x i a Slight increase in area due to control and one-bit sign extension on inputs of adder Unsigned: k bit number + k bit number k+1 bit number Signed: k+1 bit sign extended number + k+1 bit sign extended number k+1 bit number 18

10 Sequential multiplication of 2 s-complement numbers with right shifts (positive multiplier) 19 Sequential multiplication of 2 s-complement numbers with right shifts (negative multiplier) 20

11 Sequential Signed Multiplication with Left-Shifts Left shifts are not as efficient for two's complement because must sign extend multiplicand by k bits 21 Sequential Shift-and-Add Multiplier with a Carry Save Adder 22

12 Radix-2 Booth Recoding ECE 645 Computer Arithmetic Radix-2 Booth Recoding Can be used to recode unsigned multipliers or signed (two's complement) multipliers Can reduce average number of additions required Not normally used in practice due to variable delay, but serves as help to understand radix-4 Booth recoding, which is used often in practice 24

13 Radix-2 Booth Recoding j+1 j i (i.e. multiplier) 25 Radix-2 Booth Recoding Unsigned multiplication requires the leading digit in parenthesis. Two's complement multiplication does not. 26

14 Sequential multiplication of 2 s-complement numbers with right shifts using Booth s recoding 27 High-Radix Multipliers ECE 645 Computer Arithmetic

15 High-Radix Notation a Multiplicand (a k a k-2... a 1 a 0 ) r x Multiplier (x k x k-2... x 1 x 0 ) r p Product (a x) (p 2k p 2k-2... p 2 p 1 p 0 ) r 29 Radix-4, or Two-Bit-at-a-Time, Multiplication in Dot Notation 30

16 Basic Multiplication Equations p = a x k x = x i r i i=0 k p = a x = a x i r i = i=0 = x 0 ar 0 + x 1 a r 1 + x 2 a r x k a r k 31 High-Radix Shift/Add Algorithms: Right-Shift High-Radix Algorithm p = a x = x 0 ar 0 + x 1 ar 1 + x 2 ar x k ar k = = (...((0 + x 0 ar k )/r + x 1 ar k )/r x k ar k )/r = p (0) = 0 k times p (j+1) = (p (j) + x j a r k ) / r j=0..k p = p (k) 32

17 High-Radix Shift/Add Algorithms: Left-Shift High-Radix Algorithm p = a x = x 0 ar 0 + x 1 ar 1 + x 2 ar x k ar k = = (...((0 r + x k a) r + x k-2 a) r x 1 a) r + x 0 a= p (0) = 0 k times p (j+1) = (p (j) r + x k-j a) j=0..k p = p (k) 33 The multiple generation part of a radix-4 multiplier with precomputation of 3a 34

18 Example of Radix-4 Multiplication using the 3a multiple (unsigned) 35 The multiple generation part of a radix-4 multiplier Based on replacing 3a with 4a (carry into next higher radix-4 multiplier digit) and -a 36

19 Higher Radix Multiplication In radix-8, one must precompute 3a, 5a, 7a Overhead becomes prohibitive and does not help However, when we discuss CSA this may be useful 37 Radix-4 Booth Recoding Typically used for two's complement multiplication, but can also use for unsigned multiplication Radix-4 Booth recoding also called "modified" Booth recoding Goal is to reduce the number of partial products (see next slide) Increase the complexity of "multiple-forming circuits" Formerly were AND gates in normal tree multiplication Reduces number of partial products by approximately half Formerly, k-bit two's multiplier implies k partial products Now k-bit two's complement multiplier recoded into ceil(k/2) digits, so ceil(k/2) partial products 38

20 Full Tree Architecture Designs are distinguished by variations in three elements: 1. Multiple-forming circuits a Multiple- Forming Circuits... a a a Multiplier Partial products reduction tree Partial-Products Reduction Tree (Multi-Operand Addition Tree) 3. Redundant-to-binary converter Redundant result Redundant-to-Binary Converter Higher-order product bits Some lower-order product bits are generated directly 39 Radix-2 and Radix-4 Booth Recoding (1) Recoded radix-2 version y 40

21 1 41 Radix-4 Booth Recoding Examples: Unsigned x k = Always assume x = 0 2 k=12 bits, x k = 0 6 digits Unsigned: ( ) 2 = (1706) 10 = 2 * * * * * * If unsigned and x k needed, assume x k = Always assume x = k=11 bits, x k = 0 6 digits Unsigned: ( ) 2 = (682) 10 = 1 * * * * * * 4 0 Unsigned x k =0 requires ceil(k/2) digits i.e. partial products! 42

22 Radix-4 Booth Recoding Examples: Unsigned x k =1 If unsigned and x k = 1 and k is even, then need an additional digits, and assume x k+1 =x k = Always assume x = k=12 bits, x k = 1 7 digits Unsigned: ( ) 2 = (3754) 10 = 1 * * * * * * If unsigned and x k needed, assume x k = Always assume x = k=11 bits, x k = 1 6 digits Unsigned: ( ) 2 = (1706) 10 = 2 * * * * * * 4 0 Unsigned x k =1 requires ceil((k+1)/2) digits i.e. partial products! 43 Radix-4 Booth Recoding Examples: Signed x k = Always assume x = 0 2 k=12 bits, x k = 0 6 digits Signed: ( ) 2 = (1706) 10 = 2 * * * * * * If signed and x k needed, sign extend so x k =x k. In this case, x k = x k = Always assume x = k=11 bits, x k = 0 6 digits Signed: ( ) 2 = (682) 10 = 1 * * * * * * 4 0 Signed x k =0 requires ceil((k)/2) digits i.e. partial products! 44

23 Radix-4 Booth Recoding Examples: Signed x k = Always assume x = 0 0 k=12 bits, x k = 1 6 digits Signed: ( ) 2 = (-342) 10 = * * * * * If signed and x k needed, sign extend so x k =x k. In this case, x k = x k = Always assume x = k=11 bits, x k = 1 6 digits Unsigned: ( ) 2 = (-342) 10 = * * * * * 4 0 Signed x k =1 requires ceil((k)/2) digits i.e. partial products! 45 Radix-4 Unsigned and Signed Summary Unsigned If x k = 0, requires ceil(k/2) digits If x k = 1, requires ceil((k+1)/2) digits Or you can always add a '0' to the MSB of both the multiplicand and multiplier, treat the multiplication as signed, then remove the two '0' MSBs of the output Signed Requires ceil(k/2) digits 46

24 Radix-4 Booth Multiplication (Two's Complement): Sequential Right-Shift 47 Booth Recoding and Multiple Selection Logic for High-Radix Multiplication (Sequential Multiplier) 48

25 Full Tree Architecture Designs are distinguished by variations in three elements: 1. Multiple-forming circuits Now these are more complicated than AND gates a Multiple- Forming Circuits... a a a Multiplier Partial products reduction tree but there are fewer partial products 3. Redundant-to-binary converter Redundant result Partial-Products Reduction Tree (Multi-Operand Addition Tree) Redundant-to-Binary Converter Higher-order product bits Some lower-order product bits are generated directly 49 Booth Recoding and Multiple Selection Logic for High-Radix Multiplication (Tree Adder) FOR MORE INFO: PARTIAL PRODUCT 50

26 High-Radix Sequential Multipliers ECE 645 Computer Arithmetic Multiplication Architectures Area HIGH-RADIX SEQUENTIAL MULTIPLIERS 52

27 Sequential Shift-and-Add Multiplier with a Carry Save Adder 53 Radix-4 multiplication with a carry-save adder used to combine the cumulative partial product, x i a, and 2x i+1 a into two numbers 54

28 Radix-4 multiplication with a carry-save adder and Radix-4 Booth-recoding 55 Radix-4 multiplier with two carry-save adders 56

29 Radix6 multiplier with carry-save adders 57 Bit-Serial Multipliers ECE 645 Computer Arithmetic

30 Bit Serial Multipliers small area reduced pin count reduced wire length high clock rate Main disadvantage is that it is slow 59 Systolic Array Systolic array: synchronous arrays of processing elements that are interconnected by only short, local wires thus allowing very high clock rates 60

31 Semisystolic Bit-Serial Multiplier (1) 61 Semisystolic Bit-Serial Multiplier (2) a 3 x 0 a 2 x 0 a 1 x 0 a 0 x 0 a 3 x 1 a 2 x 1 a 1 x 1 a 0 x 1 a 3 x 2 a 2 x 2 a 1 x 2 a 0 x 2 a 3 x 3 a 2 x 3 a 1 x 3 a 0 x 3 a 3 0 a 2 0 a 1 0 a 0 0 a 3 0 a 2 0 a 1 0 a 0 0 a 3 0 a 2 0 a 1 0 a 0 0 a 3 0 a 2 0 a 1 0 a 0 0 p 0 p 1 p 2 p 3 p 4 p 5 p 6 p 7 62

32 Retiming k k k+n d k+n+d k+d d k k+d+n k+d+n 63 Retimed Semisystolic Bit-Serial Multiplier (1) 64

33 Retimed Semisystolic Bit-Serial Multiplier (1) a 3 0 a 2 0 a 1 0 a 0 x 0 a 3 0 a 2 0 a 1 x 0 a 0 x 1 a 3 0 a 2 x 0 a 1 x 1 a 0 x 2 a 3 x 0 a 2 x 1 a 1 x 2 a 0 x 3 a 3 x 1 a 2 x 2 a 1 x 3 a 0 0 a 3 x 2 a 2 x 3 a 1 0 a 0 0 a 3 x 3 a 2 0 a 1 0 a 0 0 a 3 0 a 2 0 a 1 0 a 0 0 p 0 p 1 p 2 p 3 p 4 p 5 p 6 p 7 65 Systolic Bit-Serial Multiplier 66

34 Modular Multiplication ECE 645 Computer Arithmetic Modular Multiplication k bits Special Cases a x a x a x = p = p H 2 k + p L p H p L p a x mod 2 k = p L a x mod 2 k = p L + p H + carry a x mod 2 k +1 = p L - p H + borrow 68

35 Modular Multiplication Special Case (1) a x mod 2 k = (p H 2 k + p L ) mod (2 k ) = = (p H (2 k mod 2 k ) + p L ) mod (2 k ) = = (p H + p L ) mod (2 k ) = = p H + p L if p H + p L < 2 k - 1 p H + p L - (2 k ) if p H + p L 2 k - 1 = p L + p H + carry carry = carry from addition p L + p H 69 Modular Multiplication Special Case (2) a x mod 2 k +1 = (p H 2 k + p L ) mod (2 k +1) = = (p H (2 k +1) + p L ) mod (2 k +1) = = (p L - p H ) mod (2 k +1) = = p L - p H if p L - p H 0 p L - p H + (2 k +1) if p L - p H < 0 = p L - p H + borrow borrow = borrow from subtraction p L + p H 70

36 Modulo (2 b ) Carry Save Adder 71 4 x 4 Modulo 15 Multiplier Mod5 CSA Divide by 16 Mod5 CSA Mod5 CPA 4 72

37 4 x 4 Modulo 13 Multiplier 73

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