CSEE 3827: Fundamentals of Computer Systems. Combinational Circuits

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1 CSEE 3827: Fundamentals of Computer Systems Combinational Circuits

2 Outline (M&K 3., 3.3, , , 4.5, 9.4) Combinational Circuit Design Standard combinational circuits enabler decoder encoder / priority encoder Code converter MUX (multiplexer) & DeMux Addition / Subtraction half and full adders ripple carry adder carry lookahead adder Shifter 2

3 Combinational circuits Combinational circuits are stateless The outputs are functions only of the inputs Inputs Combinational circuit Outputs 3

4 Hierarchical design 3-4 Big Circuit A N MX B Design small circuits to be used in a bigger circuit A B MX N ME E A 2 B 2 MX N 2 A 3 B 3 MX N 3 Smaller Circuits (a) A i N B i MX N i N N 2 N 3 ME E (b) (c) 28 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e 4

5 Enabler circuits 3-5 Output is enabled (F=X) only when input ENABLE signal is asserted (EN=) XA EN (a) F EN F A EN X A EN F (b) F A 28 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e 5

6 Decoder-based circuits Converts n-bit input to m-bit output, where n <= m <= 2 n ABC ABC A B C 3:8 decoder ABC ABC ABC ABC ABC ABC Standard Decoder: i th output =, all others =, where i is the binary representation of the input (ABC) 6

7 Decoder-based circuits So, if decoders produce minterms... A B C 3:8 decoder A B C A BC AB C ABC A B C A BC AB C ABC 7

8 Internal design of :2 decoder x 'x x :2 decoder 8

9 Hierarchical design of decoder (2:4 decoder) b :2 decoder 'b b 'b'a 'ba a :2 decoder 'a a b'a ba 2:4 decoder 9

10 Hierarchical design of decoder (3:8 decoder) c :2 decoder 'c c 'c'b'a 'c'ba 'b'a 'cb'a b a 2:4 decoder 'ba b'a 'cba ba c'b'a c'ba cb'a cba 3:8 decoder

11 Encoders Inverse of a decoder: converts m-bit input to n-bit output, where n <= m <= 2 n 28 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e T 3-7 TABLE 3-7 Truth Table for Octal-to-Binary Encoder Inputs Outputs D 7 D 6 D 5 D 4 D 3 D 2 D D A 2 A A

12 Decoder and encoder summary n{ Decoder }2 n BCD values One-hot encoding n{ n Encoder }2 Note: for Encoders - input is assumed to be just one, the rest s 2

13 Priority Encoder T 3-8 Like a regular encoder, but designed for any combination of inputs. TABLE 3-8 Truth Table of Priority Encoder Inputs Outputs D 3 D 2 D D A A V X X X X X X X X 28 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e 3

14 General code conversion 3-3 a f b e g d c (a) Segment designation (b) Numeric designation for display 28 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e 4

15 Code conversion for the a Input Output a Val W X Y Z a b c d e f g f b e g c 2 3 d A b C d E F 5

16 Multiplexers Combinational circuit that selects binary information from one of many input lines and directs it to one output line n 2 inputs output n selection bits indicate (in binary) which input feeds to the output 6

17 Truth table for a 4: mux i i i2 i3 o s s 7

18 Internal mux organization 3-26 Selector Logic S Decoder Enabler logic S 4 2 AND-OR S Decoder S I I Y Or gate passes through the nonzeroed out Ii Y I 2 Only AND gate passes through I 3 AND gates zero out unselected Ii 28 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e 8

19 In class exercise How would you implement an 8: mux using two 4: muxes? 9

20 Multiplexer truth table n{ 2 Mux n { 2^n inputs n-bit BCD value output a x x x x x x x a x b x x x x x x b x x c x x x x x c x x x d x x x x d x x x x e x x x e x x x x x f x x f x x x x x x g x g x x x x x x x h h 2

21 Demultiplexers Demux n }2 n { input n-bit BCD value 2^n outputs a a b b c c d d e e f f g g h h 2

22 Muxes and demuxes called steering logic Mux Demux merge fork 22

23 Decimal v. binary addition a4 b4 a3 b3 a2 b2 a b a b adder adder adder adder adder s4 s3 s2 s s 23

24 Ripple carry adder a4 b4 a3 b3 a2 b2 a b a b full adder full adder full adder full adder half adder a b cin cout s s4 s3 s2 s s a b c s 24

25 Subtraction w. twos complement representation Can be accomplished with a twos-complementor and an adder 25

26 In class exercise: designing an adder-subtractor 26

27 Adder/subtractor for # s in 2 s complement form 4-7 B 3 A 3 B 2 A 2 B A B A S C 3 C 2 C C FA FA FA FA C 4 S 3 S 2 S S 28 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e 27

28 Handling overflow twos-complement (5) (3) (-8) (-5) (-3) (-8) (-6) (-3) (7) (-6) (3) (-3) 28

29 Handling overflow c4 c3 c2 c c a3 a2 a a b3 b2 b b s3 s2 s s a3 b3 c3 c4 s3 overflow 29

30 Overflow computation in adder/subtractor For 2 s complement, overflow if 2 most significant carries differ C4 FA C3 FA 3

31 Ripple carry adder delay analysis Assume unit delay for all gates S = A B Cin [ S ready units after A,B and Cin ready] Cout = AB + ACin + BCin [ Cout ready units after A,B and Cin ready] a4 b4 a3 b3 a2 b2 a b a b adder adder adder adder adder s4 s3 s2 s s 3

32 Carry lookahead adder (CLA) Goal: produce an adder of less circuit depth Start by rewriting the carry function ci+ = aibi + aici + bici ci+ = aibi + ci (ai+bi) ci+ = gi + ci (pi) carry generate gi = aibi carry propagate pi = ai + bi 32

33 Carry lookahead adder (CLA) (2) Can recursively define carries in terms of propagate and generate signals c = g + cp c2 = g + cp = g + (g + cp)p = g + gp + cpp c3 = g2 + c2p2 = g2 + (g + gp + cpp)p2 = g2 + gp2 + gpp2 + cppp2 ith carry has i+ product terms, the largest of which has i+ literals If AND, OR gates can take unbounded inputs: total circuit depth is 2 (SoP form) If gates take 2 inputs, total circuit depth is + log2 k for k-bit addition 33

34 Carry lookahead adder (CLA) (3) c = c = g + cp c2 = g + gp + cpp c3 = g2 + gp2 + gpp2 + cppp2 s = a b c s = a b c s2 = a2 b2 c2 s3 = a3 b3 c3 34

35 Contraction Contraction is the simplification of a circuit through constant input values. 35

36 Contraction example: adder to incrementer What is the hardware and delay savings of implementing an incrementer using contraction? a4 b4 a3 b3 a2 b2 a b a b adder adder adder adder adder s4 s3 s2 s s Can be reduced to half-adders Incrementer circuit a S C S=a, C=a 36

37 Multi-wire notation Useful when running a bunch of bits in parallel to the same (similar place) O I C O... I C2 C k C2 Ok- Ik- Ok Ik k wires k k k wires 37

38 Shifter Circuit Shifts bits of a word: Ak-Ak-2...A2AA k Shifter n n selector bits k Bk-Bk-2...B2BB Various types of shifters Barrel: selector bits indicate (in binary) how far bits shift selector value = j, then Bi = Ai-j bits can wraparound Bi (mod 2 n ) = Ai-j (mod 2 n ) or rollout (Bi= for i<j) L/R with enable: n=2, high bit enables, low bit indicates direction (e.g., =left [Bi = Ai-], =right [Bi = Ai+]) 38

39 Barrel Shifter Design with wraparound (using MUXs) A3 A2 A A MUX MUX MUX MUX SS B3 B2 B B Basic form of design: Each Ai feeds into each MUX connecting to Bj into input (j-i) mod 4 39

40 Barrel Shifter Design with wraparound (using MUXs) A3 A2 A A MUX MUX MUX MUX B3 B2 B B Basic form of design: Each Ai feeds into each MUX connecting to Bj into input (j-i) mod 4 Selector is (i.e., 2 binary): each MUX entry 2 is selected 4

41 L/R Shift w/ Rollout A3 A2 A A MUX MUX MUX MUX SS B3 B2 B B Basic form of design: & MUX selectors (S = ) feed Ai to Bi 2 MUX selector feeds from left (Bi = Ai-), 3 MUX from right (Bi = Ai+) Note feeds ( s roll in when bits rollout) 4

42 L/R Shift w/ Rollout A3 A2 A A MUX MUX MUX MUX B3 B2 B B Basic form of design: & MUX selectors (S = ) feed Ai to Bi 2 MUX selector feeds from left (Bi = Ai-), 3 MUX from right (Bi = Ai+) Note feeds ( s roll in when bits rollout) 42

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