ECE/CS 552: Introduction To Computer Architecture 1. Instructor:Mikko H Lipasti. Fall 2010 University i of Wisconsin-Madison

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1 ECE/CS 552: Arithmetic I Instructor:Mikko H Lipasti Fall 2010 Univsity i of Wisconsin-Madison i Lecture notes partially based on set created by Mark Hill. Basic Arithmetic and the ALU Numb representations: 2 s complement, unsigned ition/subtraction /Sub ALU add, ripple carry, subtraction Carry-lookahead addition Logical opations and, or, xor, nor, shifts Ovflow Basic Arithmetic and the ALU Coved lat in the semest: Integ multiplication, division Floating gpoint arithmetic These are not crucial for the project Background Recall n bits enables 2 n unique combinations Notation: b 31 b 30 b 3 b 2 b 1 b 0 No inhent meaning f(b 31 b 0 ) => integ value f(b 31 b 0 ) => control signals Background 32-bit types include Unsigned integs Signed integs Single-precision floating point MIPS instructions (book inside cov) Unsigned Integs f(b 31 b 0 ) = b 31 x b 1 x b 0 x 2 0 Treat as normal binary numb E.g = 1 x x x x x x x 2 0 = = 213 Max f(111 11) = = 4,294,967,295 Min f(000 00) = 0 Range [0,2 32-1] => # values (2 32-1) = 2 32 ECE/CS 552: Introduction To Comput Architecture 1

2 Signed Integs 2 s complement f(b 31 b 0 ) = -b 31 x b 1 x b 0 x 2 0 Max f( ) = = Min f(100 00) = = (asymmetric) Range[-2 31,2 31-1] => # values( ) = 2 32 Invt bits and add one: e.g => => Why 2 s Complement Why not use sign-magnitude? 2 s complement makes hardware simpl Just like humans don t work with Roman numals Representation affects ease of calculation, not correctness of answ ition and Subtraction 4-bit unsigned example bit 2 s complement ignoring ovflow Subtraction A B = A + 2 s complement of B E.g add (a,b,c in ) => (c out, s) c out = two or more of (a, b, c in ) s = exactly one or three of (a,b,c in ) a b c in c out s Ripple-carry c in Just concatenate the full adds a 0 b0 a 1 b1 a 2 b2 C out a 31b31 ECE/CS 552: Introduction To Comput Architecture 2

3 Ripple-carry Subtractor A B = A + (-B) => invt B and set c in to 1 Combined Ripple-carry /Subtractor Control = 1 => subtract XOR B with control and set c in0 to control 1 C out C out a 0 b0 a 1 b1 a 2 b2 a 3 b3 a 0 b 0 a 1 b 1 a 2 b 2 a 31 b 31 opation The above ALU is too slow Gate delays for add = 32 x FA + XOR ~= 64 Theoretically, in parallel Sum 0 = f(c in, a 0, b 0 ) Sum i = f(c in, a i a 0,, b i b 0 ) Sum 31 = f(c in, a 31 a 0, b 31 b 0 ) Any boolean function in two levels, right? Wrong! Too much fan-in! Need compromise Build tree so delay is O(log 2 n) for n bits E.g. 2 x 5 gate delays for 32 bits We will consid basic concept with 4 bits 16 bits Warning: a little convoluted Need both 1 to genate carry and at least one to propagate carry Define: g i = a i * b i ## carry genate p i = a i + b i ## carry propagate Recall: c i+1 = a i * b i + a i * c i + b i * c i = a i * b i + (a i + b i ) * c i = g i + p i * c i Thefore c 1 = g 0 + p 0 * c 2 = g 1 + p 1 * c 1 = g 1 + p 1 * (g 0 + p 0 * ) = g 1 + p 1 * g 0 + p 1 * p 0 * c 3 = g 2 + p 2 * g 1 + p 2 * p 1 * g 0 + p 2 * p 1 * p 0 * c 4 = g 3 + p 3 *g 2 + p 3 *p 2 *g 1 + p 3 *p 2 *p 1 *g 0 + p 3 *p 2 *p 1 *p 0 * Uses one level to form p i and g i, two levels for carry But, this needs n+1 fanin at the OR and the rightmost AND ECE/CS 552: Introduction To Comput Architecture 3

4 c 4 4-bit Block Hiarchical for 16 bits c 15 Block g 3 p 3 a 3 b 3 g 2 p 2 a 2 b 2 g 1 p 1 a 1 b 1 g 0 p 0 a 0 b 0 P G a,b P G a,b 8-11 P G a 4-7 b 4-7 G P a 0-3 b 0-3 c 3 c 2 c 1 c 12 c 8 c 4 s 3 s 2 s 1 s 0 s s 8-11 s 4-7 s 0-3 Hiarchical CLA for 16 bits Build 16-bit add from four 4-bit adds Figure out G and P for 4 bits togeth G 0,3 = g 3 + p 3 * g 2 + p 3 * p 2 * g 1 + p 3 * p 2 * p 1 * g 0 P 03 0,3 = p 3 * p 2 * p 1 * p 0 (Notation a little diffent from the book) G 4,7 = g 7 + p 7 * g 6 + p 7 * p 6 * g 5 + p 7 * p 6 * p 5 * g 4 P 4,7 = p 7 * p 6 * p 5 * p 4 G 12,15 = g 15 + p 15 * g 14 + p 15 * p 14 * g 13 + p 15 * p 14 * p 13 * g 12 P 12,15 = p 15 * p 14 * p 13 * p 12 Basics Fill in the holes in the G s and P s G i, k = G j+1,k + P j+1, k * G i,j (assume i < j +1 < k ) P i,k = P i,j *P j+1, k G 0,7 = G 4,7 + P 4,7 * G 0,3 P 0,7 = P 0,3 * P 4,7 G 8,15 = G 12,15 + P 12,15 * G 8,11 P 8,15 = P 8,11 * P 12, 15 G 0,15 = G 8,15 + P 8,15 * G 0,7 P 0,15 = P 0,7 * P 8, 15 CLA: Compute G s and P s G 12,15 G 8,11 G 4,7 G 0,3 P 12,15 P 8,11 P 4,7 P 0,3 G 8,15 P 8,15 G 0,15 P 0,15 G 0,7 P 0,7 CLA: Compute Carries g 12 -g 15 g 8 -g 11 g 4 -g 7 g 0 -g 3 p 12 -p 15 p 8 -p 11 p 4 -p 7 p 0 -p 3 c4 c0 c 12 c 8 G 811 8,11 P 8,11 c 8 G 0,7 P 0,7 G 03 0,3 P 0,3 ECE/CS 552: Introduction To Comput Architecture 4

5 Oth s: Carry Select Two adds in parallel; with and without c in When C in is done, select correct result 0 1 Oth s: Carry Save A + B => S Save carries A + B => S, C out Use C in A + B + C => S1, S2 (3# to 2# in parallel) Used in combinational multiplis by building a Wallace Tree c b a next select 2-1 Mux select c s ing Up Many Bits f e d c b a S 0 Logical Opations Bitwise AND, OR, XOR, NOR Implement w/ 32 gates in parallel Shifts and rotates rol => rotate left (MSB->LSB) ror => rotate right (LSB->MSB) sll -> shift left logical (0->LSB) srl -> shift right logical (0->LSB) sra -> shift right arithmetic (old MSB->new MSB) S 2 S 1 Shift stage0 Mux d 7 d 6 d 1 d 0 d 0 0 shift based on 0 th bit by 0 or 1 s0 7 s0 0 s0 7 s0 6 s0 0 s0 2 s0 1 0 s0 0 0 Mux shift based on 1 st bit by 0 or 2 stage1 s1 7 s1 0 s17 s1 s1 3 s1 4 s1 0 s Mux shift based on 2 nd bit by 0 or 4 dout dout 7 dout 7 shamt0 shamt1 shamt2 Shift E.g., Shift left logical for d<7:0> and shamt<2:0> Using 2-1 Muxes called Mux(select, in 0, in 1 ) stage0<7:0> = Mux(shamt<0>,d<7:0>, 0 d<7:1>) stage1<7:0> = Mux(shamt<1>, stage0<7:0>, 00 stage0<6:2>) dout<7:0) = Mux(shamt<2>, stage1<7:0>, 0000 stage1<3:0>) For Barrel shift used wid muxes ECE/CS 552: Introduction To Comput Architecture 5

6 All Togeth Ovflow a b invt Mux carry in opation Mux result With n bits only 2 n combinations Unsigned [0, 2 n -1], 2 s complement [-2 n-1, 2 n-1-1] Unsigned > 7: => 1011 f(3:0) = a(2:0) + b(2:0) => ovflow = f(3) Carryout from MSB Ovflow ition Ovflow More involved for 2 s complement = -2: = = -2 is correct Can t just use carry-out to signal ovflow When is ovflow NOT possible? (p1, p2) > 0 and (n1, n2) < 0 p1 + p2 p1 + n1 not possible n1 + p2 not possible n1 + n2 Just checking signs of inputs is not sufficient ition Ovflow = 5 > 4: = 101 =? 3 < 0 Sum of two positive numbs should not be negative Conclude: ovflow : = 011 > 0 Sum of two negative numbs should not be positive Conclude: ovflow Ovflow = f(2) * ~(a2)*~(b2) + ~f(2) * a(2) * b(2) Subtraction Ovflow No ovflow on a-b if signs are the same Neg pos => neg ;; ovflow othwise Pos neg => pos ;; ovflow othwise Ovflow = f(2) * ~(a2)*(b2) + ~f(2) * a(2) * ~b(2) ECE/CS 552: Introduction To Comput Architecture 6

7 What to do on Ovflow? Ignore! (C language semantics) What about Java? (try/catch?) Flag condition code Sticky flag e.g. for floating point Othwise gets in the way of fast hardware Trap possibly maskable MIPS has e.g. add that traps, addu that does not Zo and Negative Zo = ~[f(2) + f(1) + f(0)] Negative = f(2) (sign bit) Zo and Negative May also want correct answ even on ovflow Negative = (a < b) = (a b) < 0 even if ovflow E.g. is 4 < 2? = 1010 (-4 2 = -6): Ovflow! Work it out: negative = f(2) XOR ovflow Summary Binary representations, signed/unsigned Arithmetic add, ripple-carry, carry lookahead Carry-select, Carry-save Ovflow, negative More (multiply/divide/fp) lat Logical Shift, and, or ECE/CS 552: Introduction To Comput Architecture 7