Overview. Arithmetic circuits. Binary half adder. Binary full adder. Last lecture PLDs ROMs Tristates Design examples

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1 Overview rithmetic circuits Last lecture PLDs ROMs Tristates Design examples Today dders Ripple-carry Carry-lookahead Carry-select The conclusion of combinational logic!!! General-purpose building blocks Critical components in processor datapaths dders Multipliers (integer, floating-point) LUs Perform most computer instructions Time space tradeoff Fast circuits usually require more logic 1 2 inary half adder inary full adder 1-bit half adder Computes sum, carry-out No carry-in = ' + ' = xor = 3 ND2 35 S Half dder 1-bit full adder Computes sum, carry-out Carry-in allows cascaded adders = xor xor = ND2 11 ND2 12 ND2 13 C in S Full dder 3

2 Full adder: lternative implementation 2-bit ripple-carry adder Multilevel logic Slower Less gates 2 s, 2 NDs, 1 OR = ( ) = + + = ( ) + Half dder xor C in S Half dder xor xor ( xor ) C in 32 ND2 11 ND2 12 ND it dder C in C in 2 Overflow 5 6 -bit ripple-carry adder/subtractor Circuit adds or subtracts 2s complement: = + ( ) = + ' + 1 Overflow 3 ' Sel ' 1 11' 0 00' 0 1 Sel 0 1 Sel 0 1 Sel S3 S2 S1 S0 Note: Can replace 2:1 muxes with gates 0 dd 1 Subtract 7 Problem: Ripple-carry delay Carry propagation limits adder speed 32 N N N ND2 11 ND2 12 ND2 13 N+1 N+2 takes two gate delays C in arrives late S0 C1 3 3 S1 S2 S3 8

3 Ripple-carry adder timing diagram One solution: Carry lookahead logic Critical delay Carry propagation = is worst case S0, C1 Valid S1, C2 Valid S2, C3 Valid S3, C Valid T0 T2 T T6 T8 Compute all the carries in parallel Derive carries from the data inputs Not from intermediate carries Use two-level logic Compute all sums in parallel Cascade simple adders to make large adders Speed improvement 16-bit ripple-carry: ~32 gate delays 16-bit carry-lookahead: ~8 gate delays Issues Complex combinational logic 0 0 C1 1 1 C2 2 2 C3 3 3 S0 C C 9 10 Full adder again Carry-lookahead logic Half dder xor Half dder xor xor ( xor ) Carry generate: G i = i i Generate carry when = = 1 Carry propagate: P i = i xor i Propagate carry-in to carry-out when ( xor ) = 1 i i i i Ci 36 ND2 37 Pi Gi 38 ND2 39 OR2 0 Si Ci+1 and in terms of generate/propagate: S i = i xor i xor C i = P i xor C i C i+1 = i i + C i ( i xor i ) = G i + C i P i 11 12

4 Carry-lookahead logic (cont d) Implementing the carry-lookahead logic Re-express the carry logic in terms of G and P C 1 = G 0 + P 0 C 0 C 2 = G 1 + P 1 C 1 = G 1 + P 1 G 0 + P 1 P 0 C 0 C 3 = G 2 + P 2 C 2 = G 2 + P 2 G 1 + P 2 P 1 G 0 + P 2 P 1 P 0 C 0 C = G 3 + P 3 C 3 = G 3 + P 3 G 2 + P 3 P 2 G 1 + P 3 P 2 P 1 G 0 + P 3 P 2 P 1 P 0 C 0 i i Ci 1 gate delay 2 gate delays 1 gate delay Logic complexity increases with adder size Implement each carry equation with two-level logic Derive intermediate results directly from inputs Rather than from carries llows "sum" computations to proceed in parallel C1 C2 G2 C3 G2 G3 C 13 Cascaded carry-lookahead adder nother solution: Carry-select adder four-bit adders with internal carry lookahead Second level lookahead extends adder to 16 bits Redundant hardware speeds carry calculation Compute two high-order sums while waiting for carry-in (C) Select correct high-order sum after receiving C [15-12] [15-12] C12 -bit dder [11-8] [11-8] -bit dder [7-] [7-] C -bit dder [3-0] [3-0] -bit dder -bit adder [7:] 0 adder low S[3-0] -bit adder [7:] 1 adder high C G3 C3 G2 C2 C1 Lookahead Carry Unit five 2:1 muxes C -it dder [3:0] -0 G3-0 S7 S6 S5 S S3 S2 S1 S

5 We've finished combinational logic... What you should know Twos complement arithmetic Truth tables asic logic gates Schematic diagrams Timing diagrams Minterm and maxterm expansions (canonical, minimized) de Morgan's theorem ND/OR to NND/NOR logic conversion K-maps, logic minimization, don't cares Multiplexers/demultiplexers PLs/PLs ROMs dders 17

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