CMPUT 329. Circuits for binary addition

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1 CMPUT 329 Parallel Adder with Carry Lookahead and ALU Ioanis Nikolaidis (Katz & Borriello) rcuits for binary addition Full adder (carry-in to cascade for multi-bit adders) Sum = xor A xor B Cout = B + A + A B = (A + B) + A B Ai Bi n Cout Sum 2

2 Full adder implementation Standard approach 6 gates 2 ORs, 2 ANDs, 2 ORs A B n S A B n A B Cout Cout = A B + n (A xor B) = A B + B n + A n 3 Ripple-carry adders Critical delay the propagation of carry from low to high order stages A B stage n @ A B A2 B2 late arriving signal two gate delays to compute Cout A3 B3 2

3 Ripple-carry adders (cont d) Critical delay the propagation of carry from low to high order stages + is the worst case addition carry must propagate through all bits S, C Valid S, C2 Valid S2, C3 Valid S3, C Valid T T2 T T6 T8 Can we generate the i-th carry without waiting for the (i-)-th carry? 5 Another view of the adder truth table Ai Bi n Sum Cout Cout is (a) when Ai Bi = OR (b) equal to n if Ai OR Bi = 6 3

4 Carry-lookahead logic Carry generate: Gi = Ai Bi must generate carry when A = B = Carry propagate: Pi = Ai xor Bi carry-in will equal carry-out here Sum and Cout can be re-expressed in terms of generate/propagate: Si = Ai xor Bi xor = Pi xor + = Ai Bi + Ai + Bi = Ai Bi + (Ai + Bi) = Ai Bi + (Ai xor Bi) = Gi + Pi 7 Carry-lookahead logic (cont d) Re-express the carry logic as follows: C = G + P C C2 = G + P C = G + P G + P P C C3 = G2 + C2 = G2 + G + P G + P P C C = G3 + P3 C3 = G3 + P3 G2 + P3 G + P3 P G + P3 P P C Implement each carry with two-level logic all the unit s inputs are directly derived from adder inputs computation of all sum outputs can proceed in parallel 8

5 Carry-lookahead implementation Adder with propagate and generate outputs Ai Bi gate delay 2 gate delays increasingly complex logic for carries C P G C P P G P G 3 3 gate delay C P P G P G G2 3 C P P P3 G P P3 G P3 G2 P3 G3 3 9 Carry-lookahead implementation (cont d) Carry-lookahead logic generates individual carries sums computed much more quickly in parallel however, cost of carry logic increases with more stages A B A B A2 B2 A3 B3 A B A B A2 B2 A3 B3 5

6 Cascaded carry-lookahead Suppose that we wish to compose a 6 bit adder from four bit adders. Note: C = G3+P3G2+P3G+P3PG+P3PPC C8 = G7+P7G6+P7P6G5+P7P6P5G+P7P6P5PC C2 = G+PG+PPG9+PPP9G8+PPP9P8C8 Equivalently all the above are: Cout = Gnew + Pnew n Where Gnew and Pnew are calculated directly from inputs of the corresponding bit adder. Carry-lookahead adder with cascaded carry-lookahead logic G = G3 + P3 G2 + P3 G + P3 P G Carry-lookahead adder P = P3 P P four-bit adders with internal carry lookahead second level carry lookahead unit extends lookahead to 6 bits A[5-2]B[5-2] C2 -bit Adder P G A[-8] B[-8] -bit Adder P G C8 A[7-] B[7-] -bit Adder P G C A[3-] B[3-] -bit Adder P G @5 P3 G3 C3 G2 C2 P G C P G C6 C C Lookahead Carry C2 = G + P G + P P C C = G + P C 2 6

7 Carry-select adder Redundant hardware (& computation) for faster carry calculation compute two high-order sums in parallel while waiting for carry-in one assuming carry-in is and another assuming carry-in is select correct result once carry-in is finally computed C8 -bit adder [7:] adder high C8 -bit adder [7:] adder low five 2: mux C -Bit Adder [3:] C C8 S7 S6 S5 S S3 S2 S S 3 Example ALU design specification M =, logical bitwise operations S S Function Fi = Ai Fi = not Ai Fi = Ai xor Bi Fi = Ai xnor Bi M =, C =, arithmetic operations F = A F = not A F = A plus B F = (not A) plus B M =, C =, arithmetic operations F = A plus F = (not A) plus F = A plus B plus F = (not A) plus B plus Comment input Ai transferred to output complement of Ai transferred to output compute OR of Ai, Bi compute NOR of Ai, Bi input A passed to output complement of A passed to output sum of A and B sum of B and complement of A increment A twos complement of A increment sum of A and B B minus A 7

8 8 5 M S S Ai Bi Fi + Example ALU bit-slice specification ALU: truth table for bit-slice 6 2 gates \S \Bi [35] [35] M M M S Bi [33] [33] [33] [33] S Ai [3] [3] [3] [3] [3] Co \Co \Co \Co \[3] \[35] Fi ALU bit-slice implementation

9 Alternative ALU bit-slice multi-level implementation S Bi S Ai M A 2 A2 first-level gates use S to complement Ai S = causes gate to pass Ai S = causes gate to pass Ai' use S to block Bi S = causes gate A to make Bi go forward as (don't want Bi for operations with just A) S = causes gate A to pass Bi use M to block M = causes gate A2 to make go forward as (don't want for logical operations) M = causes gate A2 to pass A3 O A + 3 Fi other gates for M= (logical operations, is ignored) Fi = S Bi xor (S xor Ai) = S'S' ( Ai ) + S'S ( Ai' ) + S S' ( Ai Bi' + Ai' Bi ) + S S ( Ai' Bi' + Ai Bi ) for M= (arithmetic operations) Fi = S Bi xor ( ( S xor Ai ) xor ) = + = (S xor Ai) + S Bi ( (S xor Ai) xor ) = just a full adder with inputs S xor Ai, S Bi, and 7 References Randy H. Katz & Gaetano Borriello, Contemporary Logic Design, 2/E, Pearson / Prentice Hall, 25. (ISBN ) section

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