Arithmetic Circuits Didn t I learn how to do addition in the second grade? UNC courses aren t what they used to be...

Transcription

1 rithmetic Circuits Didn t I learn how to do addition in the second grade? UNC courses aren t what they used to be... + Finally; time to build some serious functional blocks We ll need a lot of boxes The imag e cann The The image cannot image be displayed. cannot Your The The image cannot image be displayed. cannot Comp 4 Fall 25 9/29/25 L rithmetic Circuits

2 Review: 2 s Complement N bits -2 2 N- N sign bit Range: 2 N- to 2 N- binary point 8-bit 2 s complement example: = = = 42 If we use a two s-complement representation for signed integers, the same binary addition procedure will work for adding both signed and unsigned numbers. y moving the implicit binary point, we can represent fractions too:. = = = Comp 4 Fall 25 9/29/25 L rithmetic Circuits 2

3 inary ddition Here s an example of binary addition as one might do it by hand : dding two N-bit numbers produces an (N+)-bit result : :+ Carries from previous column Let s start by building a block that adds one column: F Then we can cascade them to add two numbers of any size F F F F Comp 4 Fall 25 9/29/25 L rithmetic Circuits 3

4 Designing a Full dder: From Last Time ) tart with a truth table: 2) Write down eqns for the outputs C o = C i + C i + C i + C i = C i + C i + C i + C i 3)implifing a bit C o = C i ( + ) + = C i C o = C i ( ) + = C i ( ) Comp 4 Fall 25 9/29/25 L rithmetic Circuits 4

5 For Those Who Prefer Logic Diagrams C o = C i ( ) + = C i ( ) little tricky, but only 5 gates/bit Carry Logic um Logic Comp 4 Fall 25 9/29/25 L rithmetic Circuits 5

6 ubtraction: - = + (-) Using 2 s complement representation: = ~ + ~ = bit-wise complement o let s build an arithmetic unit that does both addition and subtraction. Operation selected by control input: 3 2 ubtract 3 2 ut what about the +? F F F F 4 3 Comp 4 Fall 25 9/29/25 L rithmetic Circuits 6

7 Condition Codes esides the sum, one often wants four other bits of information from an arithmetic unit: Z (zero): result is = N (negative): result is < N- big NOR gate C (carry): indicates that add in the most significant position produced a carry, e.g., + (-) from last F V (overflow): indicates that the answer has too many bits to be represented correctly by the result width, e.g., (2 i- - )+ (2 i- - ) V = N N N + N N N -or- To compare and, perform and use condition codes: igned comparison: LT N V LE Z+(N V) 27 EQ Z! Z!! NE ~Z 5 4 GE ~(N V) 3 GT ~(Z+(N V)) Is that a NOR gate? Unsigned comparison: LTU C LEU C+Z GEU ~C GTU ~(C+Z) V = N N Comp 4 Fall 25 9/29/25 L rithmetic Circuits 7

8 T PD of Ripple-Carry dder n- n- n-2 n C F F F F F n- n-2 2 Worse-case path: carry propagation from L to M, e.g., when adding to. t PD = (t PD,XOR +t PD,ND + t PD,OR ) +(N-2)*(t PD,OR + t PD,ND ) + t PD,XOR Θ(N), to to N- to N- Θ(N) is read order N and tells us that the latency of our adder grows in proportion to the number of bits in the operands. Comp 4 Fall 25 9/29/25 L rithmetic Circuits 8

9 Faster Carry Logic Let s see if we can improve the speed by first rewriting and then reinterpreting the equations for C OUT : C OUT = + C IN + C IN = + ( + )C IN = G + P C IN where G = and P = + generate propagate To generate the Carry of the N th bit: C N = G N- + P N- C N- ctually, P was can be either + or, because the G = term of C OUT handles the only case where they differ. = G N- + P N- G N-2 + P N- P N-2 C N-2 = G N- + P N- G N-2 + P N- P N-2 G N P N-...P C IN C N in only 3 levels of logic! for P/G generation, for NDs, for final OR G P Comp 4 Fall 25 9/29/25 L rithmetic Circuits 9

10 N-it ddition in Constant Time? o if we had (N+)-input gates and didn t mind a lot of loading on the P signals, the propagation delay of adder built using P/G equation to compute C IN of each bit would be: 4 gate delays O() (independent of N) Recall large fan-in gates (many inputs) are implemented using trees (see last lecture). o for large N we expect more like O(log 2 N) gate delays. This concept does lead to some interesting adder designs: " faster ripple-carry implementations " hierarchical carry-lookahead adders Comp 4 Fall 25 9/29/25 L rithmetic Circuits

11 Carry-Lookahead dders (CL) We can build a hierarchical carry-lookahead chain by generalizing our definition of the Carry Generate/Propagate (GP) Logic. We start by dividing our addend into two parts, a higher part, H, and a lower part, L. The GP function can be expressed as follows: G HL = G H + P H G L P HL = P H P L Generate a carry out if the high part generates one, or if the low part generates one and the high part propagates it. Propagate a carry if both the high and low parts propagate theirs. G H P H G L P L G H P H GP G L P L P/G generation F C I G P F C I G P G H P HL G HL P HL Hierarchical building block st level of lookahead G H P H GP G L G HL P HL P L Comp 4 Fall 25 9/29/25 L rithmetic Circuits

12 8-bit CL (GP Generation) F G P F G P F G P F G P F G P F G P F G P F G P G H P H G L GP G HL P HL P L G H P H G L GP G HL P HL P L G H P H G L GP G HL P HL P L G H P H G L GP G HL P HL P L G 7-6 P 7-6 G 5-4 P 5-4 G 3-2 P 3-2 G - P - Log 2 (N) G H P H G L GP G HL P HL P L G 7-4 P 7-4 G H P H G L GP G HL P HL P L G H P H G L GP G HL P HL P L G 3- P 3- G 7- P 7- We can build a tree of GP units to compute the generate and propagate logic for any sized adder. For a 2 N -bit adder, we need 2 N - GP units. C = G 7 + P 7 G 6 + P 7 P 6 G 5 + P 7 P 6 P 5 G P 7...P C IN G 7- P 7- Comp 4 Fall 25 9/29/25 L rithmetic Circuits 2

13 8-bit CL (Carry Generation) C j Now, given a the value of the carry-in of the least-significant bit, we can generate the carries for every adder. c j = G j-i + P j-i c i G j- C i P j- C7 C6 C5 C4 C3 C2 C C C i Log 2 (N) G 6 c G j G j-i 4 c G j G c j-i 2 c G j G P i c j-i P i c j-i c P i 6 C P 4 C i j-i c P 2 P i j-i C c P i G 5-4 P 5-4 G 3- P 3- G j-i P j-i G j-i P j-i c j C c i c j C c i C C4 Comp 4 Fall 25 9/29/25 C6 C4 C2 C G - c j c i P - c i G j-i P j-i C c i c i C G j-i P j-i c j C c i c i Notice that the inputs on the right of each C blocks are the same as the inputs on the left of each corresponding GP block. L rithmetic Circuits 3

14 8-it CL (Complete) F G P F G P F G P F G P F G P F G P F G P F G P G H P H C j G L GP/C P L G H P H C j G L GP/C P L G H P H C j G L GP/C P L G H P H C j G L GP/C P L G HL P HL C i C i G HL P HL C i C i G HL P HL C i C i G HL P HL C i C i G H P H C j G L GP/C P L G H P H C j G L GP/C P L G HL P HL C i C i G HL P HL C i C i G H P H C j G L GP/C G HL P HL C i P L C i t PD = O(log(N)) G H P H GP G L G HL P HL P L C c G j + L c P i L C = c i G H P H C j GP/C G L P L G HL P HL C i C I Notice that we don t need the carry-out output of the adder any more. G P Comp 4 Fall 25 9/29/25 L rithmetic Circuits 4

15 Carry-kip dders Idea: full P/G equations are complicated, but P by itself is simple. o just use P to skip carry across a block of ripple-carry adders: C K-bit blocks (K=4 in figure) () Carries ripple simultaneously through each block; if block generates a carry, it appears on carry-out of block (similar to G). If carry-in is at start of operation, no spurious carry-outs will be generated. () If carry-in and P LOCK are both true, carry skips to next block (C) Carry ripples though final block. t PD = 2*[K+ (N/K 2) + K] With variable size blocks t PD O(sqrt(N)) Comp 4 Fall 25 9/29/25 L rithmetic Circuits 5

16 Carry-elect dders Idea: do two additions, one assuming carry-in is, the other assuming carry-in is. Use MUX to select correct answer when correct carry-in is known. locks on the left can be bigger (more bits) allowing more ripple time time while waiting for select With one stage: 5% more gates, but twice as fast as ripple-carry With multiple (variable-size) blocks: t PD O(sqrt(N)) Comp 4 Fall 25 9/29/25 L rithmetic Circuits 6

17 dder ummary dding is not only a common, but it is also tends to be one of the most time-critical of operations. s a result, a wide range of adder architectures have been developed that allow a designer to tradeoff complexity (in terms of the number of gates) for performance. maller / lower igger / Faster Ripple Carry Carry kip Carry elect Carry Lookahead this point we ll define a high-level functional unit for an adder, and specify the details of the implementation as necessary. dd sub dd/ub Comp 4 Fall 25 9/29/25 L rithmetic Circuits 7

18 hifting Logic hifting is a common operation that is applied to groups of bits. hifting can be used for alignment, as well as for arithmetic operations. X << is approx the same as 2*X X >> can be the same as X/2 X 7 X 6 X 5 X 4 R 7 R 6 R 5 R 4 For example: X 3 R 3 X = 2 = 2 Left hift: (X << ) = 2 = 4 Right hift: (X >> ) = 2 = igned or rithmetic Right hift: (-X >> ) = ( 2 >> ) = 2 = - X 2 X X HL R 2 R R Comp 4 Fall 25 9/29/25 L rithmetic Circuits 8

19 More hifting X 7 X 6 X 5 X 4 X 3 X 2 X X HL R 7 R 6 R 5 R 4 R 3 R 2 R R X 7 X 6 X 5 X 4 X 3 X 2 X X HL Using the same basic idea we can build left shifters of arbitrary sizes using muxes. Each shift amount requires its own set of muxes. Hum, maybe we could do something more clever. X 7 X 6 X 5 X 4 X 3 X 2 X X HL Comp 4 Fall 25 9/29/25 L rithmetic Circuits 9

20 arrel hifting X 7 X 6 X 5 X 4 X 3 X 2 X X HL R 7 R 6 R 5 R 4 R 3 R 2 R R HL HL4 T 7 T 6 T 5 T 4 T 3 T 2 T T If we connect our shift-left -two shifter to the output of our shift-left-one we can shift by,, 2, or 3 bits. nd, if we add one more shift-left-4 shifter we can do any shift up to 7 bits! o, let s put a box around it and call it a new functional block. log 2 (N) bits Left arrel hifter Y N-bits N-bits Comp 4 Fall 25 9/29/25 L rithmetic Circuits 2

21 arrel hifting with a Twist t this point it would be straightforward to construct a Right barrel shifter unit. However, a simple trick that enables a left shifter to do both RGT 7- HFT RGT Left arrel hifter Y Y 7 Y Y 6 Y 2 Y 5 Y 3 Y 4 Y 4 Y 3 Y 5 Y 2 Y 6 Y Y 7 Y Y 7- Z 7 Z 6 Z 5 Z 4 Z 3 Z 2 Z Z Comp 4 Fall 25 9/29/25 L rithmetic Circuits 2

22 oolean Operations We also need to perform logical operations on groups of bits. Which ones? NDing is useful for masking off groups of bits. ex. & = (mask selects last 4 bits) NDing is also useful for clearing groups of bits. ex. & = ( s clear first 4 bits) ORing is useful for setting groups of bits. ex. = ( s set last 4 bits) XORing is useful for complementing groups of bits. ex. ^ = ( s complement last 4 bits) NORing is useful.. Uhm, because John Hennessy says it is! ex. ~( ) = ( s complement, s clear) Comp 4 Fall 25 9/29/25 L rithmetic Circuits 22

23 oolean Unit (The obvious way) It is simple to build up a oolean unit using primitive gates and a mux to select the function. ince there is no interconnection between bits, this unit can be simply replicated at each position. The cost is about 7 gates per bit. One for each primitive function, and approx 3 for the 4-input mux. ool This is a straightforward, but not too elegant of a design. i Q i i This logic block is repeated for each bit (i.e. 32 times) Comp 4 Fall 25 9/29/25 L rithmetic Circuits 23

24 Cooler ools We can better leverage a mux s capabilities in our oolean unit design, by connecting the bits to the select lines. Why is this better? ) While it might take a little logic to decode the truth table inputs, you only have to do it once, independent of the number of bits. 2) It is trivial to extend this module to support any 2-bit logical function. (How about NND, John? ctually & / might be more useful) NOR OR XOR OR XOR i, i Q i bool ND OR Which ever way makes the most sense to you. Let s get a box around it! oolean Q I should pay more attention to those muxes Comp 4 Fall 25 9/29/25 L rithmetic Circuits 24

25 n LU, at Last We give the Math Center of a computer a special name-- the rithmetic Logic Unit. For us, it just a big box! That s a lot of stuff ub ool dd/ub idirectional arrel hifter oolean hft Math Flags V,C N Flag Comp 4 Fall 25 9/29/25 R Z Flag L rithmetic Circuits 25