Gates. Quiz 1 will cover up to and including this lecture. The book says something about NAND... maybe an in-law. Is he talking about BILL??? 6.

Transcription

1 Gates Is he talking about ILL??? The book says something about NND... maybe an in-law. WRD & HLSTED 6.4 NERD KIT Quiz will cover up to and including this lecture Fall 22 9/7/2 L4 - Gates

2 Quick Review Static discipline combinational device is a circuit element that has one or more digital inputs one or more digital outputs a functional specification that details the value of each output for every possible combination of valid input values a timing specification consisting (at minimum) of an upper bound t PD on the required time for the device to compute the specified output values from an arbitrary set of stable, valid input values input input input C If C is then copy to Y, otherwise copy to Y I will generate a valid output in no more than 2 weeks after seeing valid inputs output Y Fall 22 9/7/2 L4 - Gates 2

3 VTC and the Static Discipline V out Inverting gates Non-inverting gates V oh V ih V il V ol V ol V il V ih V oh Static Discipline requires that we avoid gray areas, which correspond to valid inputs but invalid outputs. Net result: combinational devices must have GIN and be NONLINER. The good news: CMOS gates do all this with the added bonus of no static power! V in Fall 22 9/7/2 L4 - Gates 3

4 Due to unavoidable delays Propagation delay (t PD ): n UPPER OUND on the delay from valid inputs to valid outputs. V IN V IH V IL GOL: minimize propagation delay! V OUT V OH V OL time constant τ = R PD C L < t PD Fall 22 9/7/2 < tpd time constant τ = R PU C L ISSUE: keep Capacitances low and transistors fast L4 - Gates 4

5 Contamination Delay an optional, additional timing spec INVLID inputs take time to propagate, too... V IN V IH Do Do we we really really need need tt CD? CD? V IL V OUT V OH > t CD > t CD Usually Usually not not it ll it ll be be important when when we we design design circuits circuits with with registers (coming (coming soon!) soon!) V OL If If tt CD is CD is not not specified, safe safe to to assume assume it s it s.. CONTMINTION DELY, t CD LOWER OUND on the delay from any invalid input to an invalid output Fall 22 9/7/2 L4 - Gates 5

6 The Combinational Contract t PD propagation delay t CD contamination delay > t CD Must be Note:. No Promises during 2. Default (conservative) spec: t CD = < t PD Must be Fall 22 9/7/2 L4 - Gates 6

7 Example: Timing nalysis If NND gates have a t PD = 4nS and t CD = ns t CD is the minimum cumulative contamination delay over all paths from inputs to outputs C t PD = 2 ns t CD = 2 ns Y t PD is the maximum cumulative propagation delay over all paths from inputs to outputs Fall 22 9/7/2 L4 - Gates 7

8 Functional Specifications There are many ways of specifying the function of a combinational device, for example: C If C is then copy to Y, otherwise copy to Y Concise alternatives: truth tables are a concise description of the combinational system s function. oolean expressions form an algebra in whose operations are ND (multiplication), OR (addition), and inversion (overbar). ny combinational (oolean) function can be specified as a truth table or an equivalent oolean expression! Y Truth Table C Y Y = C + C + C + C Fall 22 9/7/2 L4 - Gates 8

9 NOR: Oh yeah one last issue Z Z Recall the rules for combinational devices: Output guaranteed to be valid when all inputs have been valid for at least t PD, and, outputs may become invalid no earlier than t CD after an input changes! Many gate implementations--e.g., CMOS adhere to even tighter restrictions. Z t CD t PD Fall 22 9/7/2 L4 - Gates 9

10 What happens in this case? Z LENIENT Combinational Device: Output guaranteed to be valid when any combination of inputs sufficient to determine output value has been valid for at least t PD. Tolerates transitions -- and invalid levels -- on irrelevant inputs! Z t CD t PD Input alone is sufficient to determine the output NOR: Z Lenient NOR: Fall 22 9/7/2 Z X X Z L4 - Gates

11 We have a bag of gates. Lets design stuff! Where do we start? We have a spec. What do we do? Did I mention we have gates? F = xor 6.4 Gates We need a systematic approach for designing logic We can build NY Combinational Device can t we???? Fall 22 9/7/2 L4 - Gates

12 Slight Diversion re we sure we have all the gates we need? Just how many two-input gates are there? ND Y OR Y NND Y NOR Y Hum all of these have 2-inputs (no surprise) each with 4 combinations, giving 2 2 output cases 2 How many ways are there of assigning 4 outputs? 2 = = Fall 22 9/7/2 L4 - Gates 2

13 There are only so many gates There are only 6 possible 2-input gates some we know already, others are just silly I N P U T Z E R O N D > > X O R O R N O R X N O R N O T <= N O T <= N N D O N E How many of these gates can be implemented using a single CMOS gate? Do we need all of these gates? Nope. fter all, we describe them all using ND, OR, and NOT Fall 22 9/7/2 L4 - Gates 3

14 We can make most gates out of others > Y XOR Y Y y Y How many different gates do we really need? Fall 22 9/7/2 L4 - Gates 4

15 NNDs and NORs are universal One will do! Is that really an OR gate? = = = = = = h!, but what if we want more than 2-inputs Fall 22 9/7/2 L4 - Gates 5

16 Stupid Gate Tricks Suppose we have some 2-input XOR gates: C t pd = t cd = C nd we want an N-input XOR: 3 4 N 2 output = iff number of s input is ODD ( ODD PRITY ) N t pd = O( ) -- WORST CSE. Can we compute N-input XOR faster? Fall 22 9/7/2 L4 - Gates 6

17 I think that I shall never see a circuit lovely as N 2 log 2 N N-input TREE has O( log N ) levels... Signal propagation takes O( log N ) gate delays. Question: Can EVERY N-Input oolean function be implemented as a tree of 2-input gates? Fall 22 9/7/2 L4 - Gates 7

18 re Trees lways est? lternate Plan: Large Fan-in gates N pulldowns with complementary pullups Output HIGH if any input is HIGH = OR... Propagation delay: O( ) since each additional MOSFET adds N t pd C O(N) O(log N) N Don t be mislead by the big O stuff the constants in this case can be much smaller so for small N this plan might be the best. ~ Fall 22 9/7/2 L4 - Gates 8

19 Here s a Design pproach Truth Table C Y ) Write out our functional spec as a truth table 2) Write down a oolean expression for every in the output Y = C + C + C + C 3) Wire up the gates, call it a day, and declare success! This approach will always give us oolean expressions in a particular form: SUM-OF-PRODUCTS Fall 22 9/7/2 L4 - Gates 9

20 Straightforward Synthesis We can implement SUM-OF-PRODUCTS with just three levels of logic. INVERTERS/ND/OR Propagation delay -- No more than 3 gate delays (ignoring fan-in) C C C C Y Fall 22 9/7/2 L4 - Gates 2

21 Oh, by the way That Gate has a Name! Truth Table The gate we ve been designing for this lecture is a relatively important one: C Y C If C is then copy to Y, otherwise copy to Y Y 2-input Multiplexer C Gate symbol C (one) implementation Y Fall 22 9/7/2 L4 - Gates 2

22 Logic Simplification Can we implement the same function with fewer gates? efore trying we ll add a few more tricks in our bag. OOLEN LGER: OR rules: a + =, a + = a, a + a = a ND rules: a = a, ao =, aa = a Commutative: a + b = b + a, ab = ba ssociative: (a + b) + c = a + (b + c), (ab)c = a(bc) Distributive: a(b+c) = ab + ac, a + bc = (a+b)(a+c) Complements: bsorption: a + a =, aa = Reduction: a ( a + b) = a, ab + ab = b, a( a + b) = ab ( a + b)( a + b) = DeMorgan s Law: a + ab = a, a + ab = a + b a + b = ab, ab = a + b Fall 22 9/7/2 b L4 - Gates 22

23 oolean Minimization: n lgebraic pproach Lets (again!) simplify Y = C + C + C + C Using the identity α + α = α For any expression α and variable : Y = C + C + C + C Y = C + C + C Y = C + C Fall 22 9/7/2 L4 - Gates 23

24 Summary Timing specs t PD : upper bound on time from valid inputs to valid outputs t CD : lower bound on time from invalid inputs to invalid outputs If not specified, assume t CD = Combinational logic ny function that can be specified by a truth table or, equivalently, in terms of ND/OR/NOT (oolean expression) Lenience: optional, more demanding functional guarantee. Rarely needed; assume non-lenient logic by default. Minimally, we can get away with just 2-input NNDs or NORs Sum-of-products canonical form Comes directly from truth table 3-level implementation of any logic function Limitations on number of inputs (fan-in) increases depth Next time: logic simplification, other canonical forms Fall 22 9/7/2 L4 - Gates 24