8. Design Tradeoffs x Computation Structures Part 1 Digital Circuits. Copyright 2015 MIT EECS

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1 8. Design Tradeoffs 6.004x Computation Structures Part 1 Digital Circuits Copyright 2015 MIT EECS Computation Structures L08: Design Tradeoffs, Slide #1

2 There are a large number of implementations of the same functionality -- each represents a different point in the areatime-power space Optimization metrics: Optimizing Your Design 1. rea of the design 2. Throughput 3. Latency 4. Power consumption 5. Energy of executing a task 6. time power area vs. dvanced Micro Devices (with permission) Justin14 (CC Y-S 4.0) Computation Structures L08: Design Tradeoffs, Slide #2

3 CMOS Static Power Dissipation MOSFET Tunneling current through gate oxide: SiO 2 is a very good insulator, but when very thin (< 20Å) electrons can tunnel across. 2 Current leakage from drain to source even though MOSFET is off (aka subthreshold conduction) Leakage gets larger as difference between V TH and off gate voltage (eg, V OL in an nfet) gets smaller. Significant as V TH has become smaller. Fix: 3D FINFET wraps gate around inversion region FINFET Irene Ringworm (CC Y-S 3.0) Computation Structures L08: Design Tradeoffs, Slide #3

4 CMOS Dynamic Power Dissipation V IN moves from L to H to L V OUT moves from H to L to H V IN C V OUT E = t P(t)dt t CLK =1/f CLK Energy dissipated to discharge C: E NFET = f CLK t CLK /2 0 t CLK /2 i NFET (t)v OUT dt = f CLK C C dv OUT V OUT dt 0 dt 0 = f CLK C V OUT dv OUT V DD = f CLK C V 2 DD 2 E PFET = f CLK t CLK t CLK /2 C discharges and then recharges: i PFET (t)(v DD V OUT )dt I = C dv OUT dt Energy dissipated to recharge C: t = f CLK C C d(v CLK DD V OUT ) (V dt DD V OUT )dt t CLK /2 0 = f CLK C (V DD V OUT )d(v DD V OUT ) V DD = f CLK C V 2 DD Computation Structures L08: Design Tradeoffs, Slide #4

5 CMOS Dynamic Power Dissipation V IN moves from L to H to L V OUT moves from H to L to H V IN C V OUT t CLK =1/f CLK C discharges and then recharges: Energy dissipated = f C V DD 2 per node = f N C V DD 2 per chip where f = frequency of charge/discharge N = number of changing nodes/chip ack of the envelope : trends f ~ 1Hz = 1e9 cycles/sec N ~ 1e8 changing nodes/cycle C ~ 1fF = 1e-15 farads/node V ~ 1V 100 Watts Computation Structures L08: Design Tradeoffs, Slide #5

6 How Can We Reduce Power? [31:0] [31:0] LUFN[0] add Z V N What if we could eliminate unnecessary transitions? When the output of a CMOS gate doesn t change, the gate doesn t dissipate much power! LUFN[3:0] LUFN[1:0] boole shift LU[31:0] Z V N LUFN[2:1] cmp LUFN[5:4] Computation Structures L08: Design Tradeoffs, Slide #6

7 Fewer Transitions Lower Power [31:0] [31:0] LUFN[5] == 0 LUFN[5:4] == 10 D Q D Q LUFN[0] LUFN[3:0] add boole Z V N Signals in this region make transitions only when LU is doing a shift operation LU[31:0] LUFN[5:4] == 11 D Q Variations: Dynamically adjust t CLK or V DD (either overall or in specific regions) to accommodate workload. LUFN[1:0] Z V N LUFN[2:1] shift cmp LUFN[5:4] Must computation consume energy? See 6.5 of Notes Computation Structures L08: Design Tradeoffs, Slide #7

8 Improving Speed: dder Example n-1 n-1 n-2 n C S S S S S 0 S n-1 S n-2 S 2 S 1 S 0 Worse-case path: carry propagation from LS to MS, e.g., when adding to t PD = (N-1)*(t PD,NND3 + t PD,NND2 ) + t PD,XOR Θ(N) to N-1 to S N-1 Θ(N) is read order N and tells us that the latency of our adder grows in proportion to the number of bits in the operands Computation Structures L08: Design Tradeoffs, Slide #9

9 Performance/Cost nalysis Order Of notation: "g(n) is of order f(n)" g(n) = Θ(f(n)) g(n)=θ(f(n)) if there exist C 2 C 1 > 0 such that for all but finitely many integral n 0 C 1 f (n) g(n) C 2 f (n) Θ(...) implies both inequalities; O(...) implies only the second. g(n) = O(f(n)) Example: n 2 +2n+3 = Θ(n 2 ) since n 2 < n 2 +2n+3 < 2n 2 almost always Computation Structures L08: Design Tradeoffs, Slide #10

10 Carry Select dders Hmm. Can we get the high half of the adder working in parallel with the low half? [31:16] [31:16] [15:0] [15:0] Two copies of the high half of the adder: one assumes a carry-in of 0, the other carry-in of bit dder 16-bit dder bit dder 0 S[31:16] S[15:0] Once the low half computes the actual value of the carry-in to the high half, use it select the correct version of the high-half addition. t PD = 16*t PD, + t PD,MUX2 half of 32*t PD, ha! pply the same strategy to build 16-bit adders from 8- bit adders. nd 8-bit adders from 4-bit adders, and so on. Resulting t PD for N-bit adder is Θ(log N) Computation Structures L08: Design Tradeoffs, Slide #11

11 32-bit Carry Select dder Practical Carry-select addition: choose block sizes so that trial sums and carry-in from previous stage arrive simultaneously at MUX. [31:21] [31:21] [20:12] [20:12] [11:5] [11:5] [4:0] [4:0] C OUT SUM C OUT SUM C OUT SUM S[4:0] C OUT,S[31:21] S[20:12] Design goal: have these two sets of signals arrive simultaneously at each carry-select mux S[11:5] Select input is heavily loaded, so buffer for speed Computation Structures L08: Design Tradeoffs, Slide #12

12 Wanted: Faster Carry Logic! Let s see if we can improve the speed by rewriting the equations for C OUT : C OUT = + C IN + C IN = + ( + )C IN = + P C IN where = and P = + generate propagate ctually, P is usually defined as P = which won t change C OUT but will allow us to express S as a simple function of P and C IN : S = P C IN logic using only 3 NND2 gates! Think I ll borrow that for my circuit! Computation Structures L08: Design Tradeoffs, Slide #14

13 Carry Look-ahead dders (CL) We can build a hierarchical carry chain by generalizing our definition of the Carry enerate/propagate (P) Logic. We start by dividing our addend into two parts, a higher part, H, and a lower part, L. The P function can be expressed as follows: HL = H + P H L P HL = P H enerate a carry out if the high part generates one, or if the low part generates one and the high part propagates it. Propagate a carry if both the high and low parts propagate theirs. H P H P L P/ generation H L HL P HL Hierarchical building block 1 st level of lookahead H P H P HL P HL L Computation Structures L08: Design Tradeoffs, Slide #15

14 8-bit CL (generate & P) H P H L P HL P HL H P H L P HL P HL H P H P HL P HL L H P H P HL P HL L 7-6 P P P P 1-0 Θ(log N) H P H P HL P HL H P H P HL P HL L 7-4 P 7-4 L H P H P HL P HL L 3-0 P P 7-0 We can build a tree of P units to compute the generate and propagate logic for any sized adder. ssuming N is a power of 2, we ll need N-1 P units. This will let us to quickly compute the carry-ins for each! Computation Structures L08: Design Tradeoffs, Slide #16

15 8-bit CL (carry generation) Now, given a the value of the carry-in of the leastsignificant bit,we can generate the carries for every adder. c H = L + c in c L = c in C7 C6 C5 C4 C3 C2 C1 C0 Θ(log N) 6 L L L c H P c c L c L c 6 C P 4 C in L P c 2 P in L C P c 0 in 5-4 P P 3-0 c H C c in c L c H C C4 c in c L C0 L c H L L c H C c L c in C0 L c H c in c L C6 C4 1-0 C2 c H C0 P 1-0 C6 = 5-4 +P 5-4 C4 C4 = 3-0 +P 3-0 C0 C Notice that the inputs on the left of each C blocks are the same as the inputs on the right of each corresponding P block Computation Structures L08: Design Tradeoffs, Slide #17

16 8-bit CL (complete) H P H C j L P/C H P H C j L P/C H P H C j L P/C H P H C j L P/C C i HL P HL C i C i HL P HL C i C i HL P HL C i C i HL P HL C i H P H C j L P/C H P H C j L P/C C i HL P HL C i C i HL P HL C i H P H C j L C i P/C HL P HL C i t PD = Θ(log N) H P H P L HL P HL C0 c H + L = c L C c i H P H C H P/C L C L HL P HL C in Notice that we don t need the carry-out output of the adder any more. To learn more, look up Kogge-Stone adders on Wikipedia Computation Structures L08: Design Tradeoffs, Slide #18

17 Hey, that looks like an ND gate inary Multiplication* The inary Multiplication Table * ctually unsigned binary multiplication * x i called a partial product Multiplying N-digit number by M-digit number gives (N+M)-digit result Easy part: forming partial products (just an ND gate since I is either 0 or 1) Hard part: adding M N-bit partial products Computation Structures L08: Design Tradeoffs, Slide #20

18 Combinational Multiplier b 0 S b 1 H H H b 2 S H b 3 H z 7 z 6 z 5 z 4 z 3 z 2 z 1 z 0 Latency = Θ(N) Throughput = Θ(1/N) Hardware = Θ(N 2 ) Computation Structures L08: Design Tradeoffs, Slide #21

19 2 s Complement Multiplication Step 1: two s complement operands so high order bit is 2 N-1. Must sign extend partial products and subtract the last one Step 3: add the ones to the partial products and propagate the carries. ll the sign extension bits go away! X3 X2 X1 X0 * Y3 Y2 Y1 Y X3Y0 X3Y0 X3Y0 X3Y0 X3Y0 X2Y0 X1Y0 X0Y0 + X3Y1 X3Y1 X3Y1 X3Y1 X2Y1 X1Y1 X0Y1 + X3Y2 X3Y2 X3Y2 X2Y2 X1Y2 X0Y2 - X3Y3 X3Y3 X2Y3 X1Y3 X0Y Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 X3Y0 X2Y0 X1Y0 X0Y0 + X3Y1 X2Y1 X1Y1 X0Y1 + X3Y2 X2Y2 X1Y2 X0Y2 + X3Y3 X2Y3 X1Y3 X0Y Step 2: don t want all those extra additions, so add a carefully chosen constant, remembering to subtract it at the end. Convert subtraction into add of (complement + 1). X3Y0 X3Y0 X3Y0 X3Y0 X3Y0 X2Y0 X1Y0 X0Y X3Y1 X3Y1 X3Y1 X3Y1 X2Y1 X1Y1 X0Y X3Y2 X3Y2 X3Y2 X2Y2 X1Y2 X0Y X3Y3 X3Y3 X2Y3 X1Y3 X0Y3 + 1 = ~ Step 4: finish computing the constants X3Y0 X2Y0 X1Y0 X0Y0 + X3Y1 X2Y1 X1Y1 X0Y1 + X3Y2 X2Y2 X1Y2 X0Y2 + X3Y3 X2Y3 X1Y3 X0Y Result: multiplying 2 s complement operands takes just about same amount of hardware as multiplying unsigned operands! Computation Structures L08: Design Tradeoffs, Slide #22

20 2 s Complement Multiplier b 0 1 b 1 H b 2 H 1 b 3 H H z 7 z 6 z 5 z 4 z 3 z 2 z 1 z Computation Structures L08: Design Tradeoffs, Slide #23

21 Increase Throughput With Pipelining gotta break that long carry chain! b 0 b 1 H H b 2 H b 3 H z 7 z 6 z 5 z 4 z 3 z 2 z 1 z 0 efore pipelining: Throughput = ~1/(2N) = Θ(1/N) fter pipelining: Throughput = ~1/N = Θ(1/N) Computation Structures L08: Design Tradeoffs, Slide #25

22 Carry-save Pipelined Multiplier Observation: Rather than propagating the carries to the next column, they can instead be forwarded onto the next column of the following row H H H b 0 b 1 b 2 b 3 H H H H H Latency = Θ(N) Throughput = Θ(1) Hardware = Θ(N 2 ) z 7 z 6 z 5 z 4 z 3 z 2 z 1 z Computation Structures L08: Design Tradeoffs, Slide #26

23 Reduce rea With Sequential Logic ssume the multiplicand () has N bits and the multiplier () has M bits. If we only want to invest in a single N-bit adder, we can build a sequential circuit that processes a single partial product at a time and then cycle the circuit M times: S N N S N-1 S 0 LS P Carry-save M bits + N+1 NC xn 1 N Init: P 0, load & Repeat M times { P P + ( LS ==1? : 0) shift S N,P, right one bit } Done: (N+M)-bit result in P, N+1 Sum bits and N saved carries T PD = Θ(1) for carry-save (see previous slide), but adds Θ(N) cycles & Θ(N) hardware Latency = Θ(N) Throughput = Θ(1/N) Hardware = Θ(N) Computation Structures L08: Design Tradeoffs, Slide #27

24 Summary Power dissipation can be controlled by dynamically varying T CLK, V DD or by selectively eliminating unnecessary transitions. Functions with N inputs have minimum latency of O(log N) if output depends on all the inputs. ut it can take some doing to find an implementation that achieves this bound. Performing operations in slices is a good way to reduce hardware costs (but latency increases) Pipelining can increase throughput (but latency increases) symptotic analysis only gets you so far factors of 10 matter in real life and typically N isn t a parameter that s changing within a given design Computation Structures L08: Design Tradeoffs, Slide #29