Full Adder Ripple Carry Adder Carry-Look-Ahead Adder Manchester Adders Carry Select Adder

Transcription

1 Outline E 66 U Resources: dders & Multipliers Full dder Ripple arry dder arry-look-head dder Manchester dders arry Select dder arry Skip dder onditional Sum dder Hybrid Designs leksandar Milenkovic milenka@ece.uah.edu Web: Full dder Inputs data inputs, carry in in Outputs sum S carry out out Full dder S in out in ( ) in ( ) out S in in in in ( ) in ( ) in in in in out ( ) in in S

2 Full dder Transmission-ate dder () S in ( in) out Vdd in > - > T is open > out - > - > T is closed > out in in out ND in in in Vdd S ND T XOR > - > T is closed > out > - > T is open > out - ND T XNOR XNOR(,) 5 6 Transmission-ate dder () in S in > S in in > S in in in SUM out out in ( ) in ( ) Ripple arry dder - R () Method [i] [i]*[i] [i] [i] [i] [i] [i] [i]*[i-] S[i] [i] [i-] Method [i] [i]*[i] [i] [i] [i] [i] [i] [i]*[i-] S[i] [i] [i] [i-] [i] [i] [i] [i] [i] [i] S[i]

3 Ripple arry dder - R () Replace ND-OR pair with fast -inputs NND gates R delay is proportional to n and is limited by the propagation of the carry signal through all of the stages [i] [i] [i] [i] [i] [i] [i] [i] [i] [i] [i] S[i] S[i] 9 Ripple arry dder - R () i i i (i i) i i (i i) (i i i) i i i i ( i i i i i i) (i i i) i i i i i i i i i (i i) i i (i i) (i i) i i i i i i i i i i i i i i i i i i i Used in odd stages! i i i or i i i Used in even stages! Ripple arry dder - R () arry-look-head dder L () arry equations [i] [i]*[i] [i]*[i] or [i] ([i] [i])*([i] [i]) [i] NOT([i]) Even stages [i] [i]*[i]*[i] [i] [i] [i] [i] [i]*[i] Odd stages [i] [i]*[i]*[i] [i] [i]*[i] [i] [i] [i] Inputs to stage zero: [] [] [i] [i] [i] [i] [i] [i] [i] Even stages S[i] [i] [i] Odd stages S[i] [i] [i] [i] Idea: speed up carry computation i i i* i ropagate: i i i if i, then carry from (i-)th stage is propagated enerate: i i * i if i there is carry out i i i Si i i i i i i i i i i i i (i i i) i i i i i i i i i i i (i i i) i i i i i i i i i i

4 arry-look-head dder L () enerator arry enerate lock Sum enerator S S S S arry-look-head dder L () Domino implementation (Dynamic arry ates) 5 arry-look-head dder L () ) ( ) ( ) ( 6 arry-look-head dder L (5) : : S : - - S S S

5 rent-kung L Manchester dder ircuits () a) lookahead terms b) L cell c) cells can be rearranged into tree d) simplified representations for part a) e) simplified representation for part c) f) lookahead logic for -bit adder g) rent-kung adder Reduces delay, increases the regularity, reduces the number of unnecessary switching events (power) i i i i i i i i i i i i i i Manchester dder ircuits () i i i i Dynamic Stage Static Stage MUX stage i i i i -bit Manchester dder i i i i i i i i i i i i i i i i i i S i i i i i > i i i > i i 9 i i i i

6 arry ypass arry Select dder () ( ) ompute versions of the addition with different carry-ins, one assuming that the carry-in is and another assuming that it is ( ) arry Select dder () arry Skip dder: Motivation : : S : : : S : S : M S : : : S : S : M S : 5: 5: S 5: S 5: 6 S 5: M 6 omputing - is much simpler than computing - : : : : 5: 5: Let s compute only -! 6 6 6

7 arry Skip dder ractical only if the carry-in signals can be easily cleared at the start of each operation e.g. precharging MOS : : : : : : 5: 5: S : : S : arries begin rippling simultaneously through each block; If any block generates a carry, then the carry out will be true, even the carry-in may not be not true yet. If at the start of each add operation the carry-in to each block is, then correct carry-outs will be generated carry-out can be thought of as if it is the signal : S : S 5: 5 6 arry Skip dder: nalysis ssume it takes time unit for signal to propagate through two logic level n bits wide adder blocks of size k It will take k units for a carry to ripple through a block of size k ritical path k units for the first block n/k units to skip the blocks k units to ripple through the last block Increase the efficiency by varying the blocks size bits (,,,,,): Delay bits (, 5, 6, 5, ): Delay 9 6 onditional Sum dder () Si i i i i i i (i i) i Si i i i i Si i i i i XNOR( i, i) i i i (i i) i i i i i (i i) i i onditional Sum dder ()

8 9 onditional Sum dder () S S i Si i Si i Si i Si i Si i Si Hybrid Designs: n Example ombine L (arry Look-head) with R