ECE 645: Lecture 3. Conditional-Sum Adders and Parallel Prefix Network Adders. FPGA Optimized Adders

Transcription

1 ECE 645: Lecture 3 Conditional-Sum Adders and Parallel Prefix Network Adders FPGA Optimized Adders

2 Required Reading Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Design Chapter 7.4, Conditional-Sum Adder Chapter 6.4, Carry Determination as Prefix Computation Chapter 6.5, Alternative Parallel Prefix Networks

3 Add-Add-Multiplex Carry Select Adder

4 Two-level k-bit Carry Select Adder

5 Add-Add-Multiplex (AAM) Carry Select Adder + stands for the Ripple Carry Adder CCC stands for the Carry Computation Circuit CR stands for the Carry Recovery Circuit

6 Carry Computation Circuit

7 Carry Recovery Circuit

8 Carry & Control Logic in Virtex 4

9 Carry & Control Logic in Virtex 5

10 Homework 2 - Bonus Analytical Problem: Find analytically an optimal value of the word size, w, for which a 1024-bit AAM Carry Select Adder has the smallest latency. Implementation Problem: Find experimentally an optimal value of the word size, w, for which a 1024-bit AAM Carry Select Adder has the smallest latency. 10

11 Conditional-Sum Adders

12 One-level k-bit Carry-Select Adder

13 Two-level k-bit Carry Select Adder

14 Conditional Sum Adder Extension of carry-select adder Carry select adder One-level using k/2-bit adders Two-level using k/4-bit adders Three-level using k/8-bit adders Etc. Assuming k is a power of two, eventually have an extreme where there are log 2 k-levels using 1-bit adders This is a conditional sum adder 14

15 Conditional Sum Adder: Top-Level Block for One Bit Position 15

16 Three Levels of a Conditional Sum Adder x i+3 y i+3 x i+2 y i+2 x i+1 y i+1 x i y i branch point c=1 c=0 2 2 c=1 c=0 2 2 c=1 c= bit conditional sum block c=1 c=0 2 2 concatenation c=1 3 c=0 3 c=1 3 c= c=1 5 c= block carry-in determines selection 16

17 16-Bit Conditional Sum Adder Example 17

18 Conditional Sum Adder Metrics 18

19 Parallel Prefix Network Adders

20 Parallel Prefix Network Adders Basic component - Carry operator (1) g p B B B g p g p g = g + g p p = p p (g, p) = (g, p ) (g, p ) = (g + g p, p p ) 20

21 Parallel Prefix Network Adders Basic component - Carry operator (2) g p B B overlap okay! B g p g p g = g + g p p = p p (g, p) = (g, p ) (g, p ) = (g + g p, p p ) 21

22 Properties of the carry operator Associative [(g 1, p 1 ) (g 2, p 2 )] (g 3, p 3 ) = (g 1, p 1 ) [(g 2, p 2 ) (g 3, p 3 )] Not commutative (g 1, p 1 ) (g 2, p 2 ) (g 2, p 2 ) (g 1, p 1 ) 22

23 Parallel Prefix Network Adders Major concept Given: (g 0, p 0 ) (g 1, p 1 ) (g 2, p 2 ). (g k-1, p k-1 ) Find: (g [0,0], p [0,0] ) (g [0,1], p [0,1] ) (g [0,2], p [0,2] ) (g [0,k-1], p [0,k-1] ) c i = g [0,i-1] + c 0 p [0,i-1] block generate from index 0 to k-1 23

24 Similar to Parallel Prefix Sum Problem Parallel Prefix Sum Problem Given: Find: x 0 x 1 x 2 x k-1 x 0 x 0 +x 1 x 0 +x 1 +x 2 x 0 +x 1 +x x k-1 Parallel Prefix Adder Problem Given: x 0 x 1 x 2 x k-1 Find: x 0 x 0 x 1 x 0 x 1 x 2 x 0 x 1 x 2 x k-1 where x i = (g i, p i ) 24

25 Parallel Prefix Sums Network I 25

26 Parallel Prefix Sums Network II (Brent-Kung) 26

27 8-bit Brent-Kung Parallel Prefix Network x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 4 bit B-K PPN s 7 s 6 s 5 s 4 s 3 s 2 s 1 s 0 27

28 4-bit Brent-Kung Parallel Prefix Network x 7 x 5 x 3 x 1 2 bit B-K PPN s 7 s 5 s 3 s 1 28

29 8-bit Brent-Kung Parallel Prefix Network Adder x 7 y 7 x 6 y 6 x 5 y 5 x 4 y 4 x 3 y 3 x 2 y 2 x 1 y 1 x 0 y 0 GP GP GP GP GP GP GP GP g 7,p 7 g 6,p 6 g 5,p 5 g 4,p 4 g 3,p 3 g 2,p 2 g 1,p 1 g 0,p 0 c c c c c c c critical path c c c c g [0,7] p [0,7] g [0,6] p [0,6] g [0,5] p [0,5] g [0,4] p [0,4] g [0,3] p [0,3] g [0,2] p [0,2] g [0,1] p [0,1] g [0,0] p [0,0] c 0 c 8 C C C C C C C C c 7 p 7 c 6 p 6 c 5 p 5 c 4 p 4 c 3 p 3 c 2 p 2 c 1 p 1 p 0 S S S S S S S S s 7 s 6 s 5 s 4 s 3 s 2 s 1 s 0 29

30 Critical Path GP g i = x i y i p i = x i y i 1 gate delay c g = g + g p p = p p 2 gate delays C c i+1 = g [0,i] + c 0 p [0,i] 2 gate delays S s i = p i c i 1 gate delay 30

31 Brent-Kung Parallel Prefix Graph for 16 Inputs 31

32 Kogge-Stone Parallel Prefix Graph for 16 Inputs 32

33 Parallel Prefix Network Adders Comparison of architectures Network 2 Brent-Kung Hybrid Kogge-Stone Delay(k) 2 log 2 k - 2 log 2 k+1 log 2 k Cost(k) 2k log 2 k k/2 log 2 k k log 2 k - k + 1 Delay(16) Cost(16) Delay(32) Cost(32)

34 Latency vs. Area Tradeoff 34

35 Hybrid Brent-Kung/Kogge-Stone Parallel Prefix Graph for 16 Inputs 35

36 Parallel Prefix Sums Network I 36

37 Parallel Prefix Sums Network I Cost (Area) Analysis Cost = C(k) = 2 C(k/2) + k/2 = = 2 [2C(k/4) + k/4] + k/2 = 4 C(k/4) + k/2 + k/2 = =. = = 2 log 2 k-1 C(2) + k/2 (log 2 k-1) = = k/2 log 2 k C(2) = 1 Example: C(16) = 2 C(8) + 8 = 2[2 C(4) + 4] + 8 = = 4 C(4) + 16 = 4 [2 C(2) + 2] + 16 = = 8 C(2) + 24 = = 32 = (16/2) log

38 Parallel Prefix Sums Network I Delay Analysis Delay = D(k) = D(k/2) + 1 = = [D(k/4) + 1] + 1 = D(k/4) = =. = = log 2 k D(2) = 1 Example: D(16) = D(8) + 1 = [D(4) + 1] + 1 = = D(4) + 2 = [D(2) + 1] + 2 = = 4 = log

39 Parallel Prefix Sums Network II (Brent-Kung) 39

40 Parallel Prefix Sums Network II Cost (Area) Analysis Cost = C(k) = C(k/2) + k-1 = = [C(k/4) + k/2-1] + k-1 = C(k/4) + 3k/2-2 = =. = = C(2) + (2k - 2k/2 (log 2 k-1) ) - (log 2 k-1) = = 2k log 2 k C(2) = 1 Example: C(16) = C(8) = [C(4) + 8-1] = = C(2) = = 26 = log

41 Parallel Prefix Sums Network II Delay Analysis Delay = D(k) = D(k/2) + 2 = = [D(k/4) + 2] + 2 = D(k/4) = =. = = 2 log 2 k - 1 D(2) = 1 Example: D(16) = D(8) + 2 = [D(4) + 2] + 2 = = D(4) + 4 = [D(2) + 2] + 4 = = 7 = 2 log

42 High-Radix Parallel Prefix Network Adders (GMU CERG Research)

43 Traditional Parallel-Prefix Network Adder

44 Kogge-Stone Parallel-Prefix Network

45 Brent-Kung Parallel-Prefix Network

46 High-Radix Parallel-Prefix Network Adder

47 Generate-Propagate-Sum (GPS) Unit

48 Sum Unit

49 Modular Addition

50 High-Radix Parallel-Prefix Network Modular Adder

51 Test Circuit for Benchmarking Adders and Modular Adders