The logic is straightforward. Adding two 0s will result in 0. Adding two 1s results in 10 where 1 is the carry bit and 0 is the sum bit.

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1 Adders Half adders Half adders represent the smallest block for adding in digital computers. What they do is very simple: they add two bits, producing a sum and a carry. The logic is straightforward. Adding two 0s will result in 0. Adding two s results in 0 where is the carry bit and 0 is the sum bit. The operation can be tabulated as follows: = = + 0 = + = 0 Inputs Outputs A B S Truth table for a half adder The expressions for the carry and sum bits are A B and S A B. The circuit for the half adder is the following: OFFTIME =.5uS B ONTIME =.5uS LK STARTAL = OPPAL = 0 UA 74LS08 OFFTIME = us A ONTIME = us LK STARTAL = OPPAL = 0 UA 74LS86A S ircuit for a half adder The half adder consists of an AND gate that provides the carry bit and an XOR gate that provides the sum bit.

2 In high-level schematics, the half adder is often shown as a block: Half adder block The waveforms for the half adder reflect the logic previously outlined: A: B: UA:Y UA:Y 0s 0.5us.0us.5us.0us Time Waveforms for a half adder The half adder produces a carry bit only when both input bits are and it produces a sum bit only if one of the input bits is.

3 Full adders Full adders are the next step after half adders. What they do is also simple: they add three bits, producing a sum bit and a carry bit. The logic is straightforward. Adding two 0s results in 0. Adding two s results in 0 where is the carry bit and 0 is the sum bit. Adding three s produces, for carry bit and for sum bit = = = = = = = = One of the bits is a carry-in bit that comes from a previous stage. That bit is shown in the third column. The carry-out bit that results from the operation is passed on to a higher level within the adder. The operation can be tabulated as follows: Inputs Outputs A B in out S Truth table for a full adder The expressions for the carry and sum bits are: A B A B out in S A B in

4 The circuit for the full adder is the following: OFFTIME =.5uS ONTIME =.5uS LK STARTAL = OPPAL = 0 OFFTIME = us B ONTIME = us LK STARTAL = OPPAL = 0 UA 74LS86A UA 74LS86A S OFFTIME = us A ONTIME = us LK STARTAL = OPPAL = 0 U4A UA 74LS08 U5A 74LS 74LS08 ircuit for a full adder The full adder consists of XOR gates, AND gates and OR gate. The XOR gates provide the sum bit while the AND/OR gate group provides the carry bit. It s worth noting that UA and U4A are essentially a half adder just like UA and UA so a full adder is made of half adders and OR gate. In high-level schematics, the full adder is often shown as a block: Block for a full adder The waveforms for the full adder reflect the logic previously outlined: A: B: : U5A:Y UA:Y 0s 0.5us.0us.5us.0us.5us.0us.5us 4.0us Time Waveforms for a full adder 4

5 Multiple-bit adders Adding two bits is very simple. Applications are much more complex and require several bits to be are added. Therefore, several full adder blocks are used to obtain additions for arrays of bits. For this purpose, ripple carry adders and carry look-ahead adders have been invented. 4-bit ripple carry adder The following is an example of a 4-bit ripple carry adder. 4-bit ripple carry adder block diagram This is the simplest multiple-bit adder available. It is very basic since each full adder block connects to the next one in series. However, this adder has a major disadvantage which is the propagation delay of the carry bits to obtain the final addition. The carry bits, in fact, ripple through the adder from right to left. This is why this adder is called ripple carry adder. This adder is obviously impractical if it is to be used in time-critical applications. Alternatives to the ripple carry adder exist. These alternatives speed up addition by using a separate and dedicated set of gates. 5

6 4-bit carry look-ahead adder In order to circumvent the problem of the propagation delay associated to the ripple carry adder, engineers developed strategies to compute carry bits ahead of time by using propagate and generate bits (P and G). These bits are then combined in successive expressions in order to derive propagate group and generate groups (PG and GG). PG and GG are useful if several blocks of the 4-bit carry look-ahead adder are used. 4-bit carry look-ahead adder block diagram The adder shown above adds an array of 4 bits (A 0 through A ) to another array of 4 bits (B 0 through B ). The result of the addition is provided by bits S 0 through S and 4. A propagate bit P corresponds to the XORing of two bits. The generate bit G corresponds to the ANDing of two bits. The general expression for the carry bits and the derived one for 4 are: Expressions for PG and GG are: 6

7 6-bit carry look-ahead adder By using 4 instances of the previously presented 4-bit carry look-ahead adder, a 6-bit carry look-ahead adder can be constructed. 6-bit carry look-ahead adder block diagram The adder shown above adds an array of 6 bits (A 0 through A 5 ) to another array of 4 bits (B 0 through B 5 ). The result of the addition is provided by bits S 0 through S 5 and bit carry look-ahead adder By using 4 instances of the previously presented 6-bit carry look-ahead, a 64-bit carry look-ahead adder can be constructed. 64-bit carry look-ahead adder block diagram The adder shown above adds an array of 64 bits (A 0 through A 6 ) to another array of 64 bits (B 0 through B 6 ). The result of the addition is provided by bits S 0 through S 6 and 64. 7