CS221: Digital Design Data Path Components Adder

Transcription

1 CS221: Digital Design Data Path Coponents Adder Dr. A. Sahu DeptofCop.Sc.&Engg. Indian Institute of Technology Guwahati

2 Outline Adder: Basic Model Carry Propagation and Generation MachesterAdder Carry Skip Adder Carry Select Adder Carry Look Ahead Adder CarrySaveAdder:MultipleOperand

3 N Bit Ripple Carry Adder: Series of FA Cells To add two n bit nubers A n-1 B n-1 A 2 B 2 A 1 B 1 A 0 B 0 FA C n... n FA FA FA C 0 S n-1 S 2 S 1 S 0 Adder delay = Tc * n Tc = (C in to C out delay) ofafa A B C out FA C in Su 3

4 Adder Schees Step1: Obtain carries (Carry at idepends on j < i), Non trivial to do fast Step2: Copute su bits (local function) X Y C 0 =C in C out =C n y n 1 x n 1 yi y 1 x i 1 x 0 x 1 y 0 Step1: Obtain Carries Step2: Coputer Su s n 1 s i s 1 s 0 4

5 Matheatically:C &S i i C i =FuncC(x i 1,..,x 0, y i 1,..,y 0, c in ) S =FuncS(x, y, c ) i i i i = ( x i + y i + c i ) od 2 5

6 Ripple Carry Adder Analysis i x i C in =0 y i P K P P P G P P P K C i Case X i Y i X i +Y i C i+1 Coent Kill (K i =1) Kill/Stop C in /C out =0 Propagate P i =1 011 C i Propagate C in 101 C i C out =C in Generate (G i =1), GenerateC out, C out =1 6

7 Propagate,Generate& Kill Case 1 (Kill): k i = x i y i = (x i +y i ) i i i i i Case 2 (Propagate): p i = x i XOR y i Case 3(Generate): g i = x i + y i Then c i+1 = g i + p i c i = x i y i + (x i XOR y i ) c i Alternative (sipler) expression: c i+1 = g i + a i c i Since a i = k i, we call it "alive" 7

8 ReducingAdderDelay Ripple Carry Adder: N(t c )+ax(t c,t s ) Reducing Carry Delay t c : Manchester Switch Changing linear factor to saller N/k or logn Carry Look Ahead, Carry Skip, Carry Select, Conditional Su Adder Including a copetition signal: addition always ay not be the worst case. Changing nuber representation: Carry Saved Adder 8

9 Switched Carry Ripple (Manchester) Adder Idea: Fast circuit to propagating carry chain x i +y i G i P i K i C i Ci

10 ChainControlSwitchModule Control x i y i Carry Control GKP g i k i 1 0 p i C i+1 C i 10

11 ManchesterAdder(MRCA) Delay:t sw +(n 1)*t p Here t p < t c, so total delay is less Y n 1 X n 1 Y i X i Y 1 X 1 Y0 X0 CC CC CC CC C in S n 1 S i S 1 S 0 11

12 CarrySkipAdder Saller odification to Ripple Carry Adder Reduce worst case delay by reducing the nuber of FA cell through carry has to Propagate Divide n bits in to (n/) groups of bits Ifsuofgroupis2 1thencarryispropagated1 Carry is propagated when it propagated by all the bits of the groups P j = p j0 p j1 p j2..p j 1 C in,j+1 = C out, j. P j + C in,j +P j 12

13 CarrySkipExaple P=0 P=1 P=1 P=0 P=1 P= C i P C j+1 C j 13

14 CSK Module If Pj=1: siply skip the group j,c in,j+1 =C in,j P j x j y j C in,j+1 M0M 0 U X 1 C out M bit RCA Group J C in Module n 1 Module i s j Module 1 Module 0 CSK Module CSK Module CSK Module CSK Module 14

15 CarrySkipPath skipped Skip is Data Dependent 15

16 For All Groups: For Both Carry =0 and carry=1su&carryis already calculated Carry Select Adder FA FA FA FA Siply select Carry & Su based on carry input FA FA FA FA 16 Skip is Data Independent

17 Thanks