CS221: Digital Design. Dr. A. Sahu. Indian Institute of Technology Guwahati

Size: px
Start display at page:

Download "CS221: Digital Design. Dr. A. Sahu. Indian Institute of Technology Guwahati"

Transcription

1 CS221: Digital Design QMLogicMinimization Minimization Dr. A. Sahu DeptofComp.Sc.&Engg. Indian Institute of Technology Guwahati 1

2 Outline Quine McCluskey(QM) Logic Minimization Examples Writing C/C++ program for QM Method 2

3 BCDAdder(TwoLevel) Treat as 9 input & 5 output functions Generate TthTbl Truth Table for each outputs t Solve each function using KMAP/QM Method Only Two Level: No carry Propagation Ci a1 b1 c1 d1 a2 b2 c2 d2 Adder 2 Level a b c d Co 3

4 Quine McCluskeyMethod for Minimization KMAP methods was practical for at most 6 variable functions Larger number of variables: need method that can be applied to computer based minimization Quine McCluskey method For example: m(0,1,2,3,5,7,13,15)

5 QMMethod Method PhaseI:findingPis Pis Tabular methods: Grouping and combining PhaseII:CoversminimalPIs PIs 5

6 QM Method QM Method Mintermsthat differ in one variable s value can be combined. Thus we list our mintermsso that they are in groups with each group having the same number of 1s. So the first step is ordering the minterms according to their number of 1s (0 cube list) only mintermsresiding in adjacent groups have the chance to be combined.):

7 QM Method m (0,1,2,3,5,7,13,15 ) 0_Cube

8 QM Method: Combining Adjacent Compare mintermsof a group with those ofanadjacentonetoform1 adjacent one form 1 cube cubelist. When doing the combining, we put checkmark alongside the mintermsin the 0 cubelistthathavebeencombined. that have been combined.

9 QM Method 1_Cube 0_Cube , , , ,4

10 QM Method: Combining Adjacent Do same combination of comparing adjacent group minterms To form 2 cubes, 3 cubes and so on. Ol Only mintermsof it adjacent groups have the chance of being combined Which have an in the same position.

11 QM Method 1_Cube _Cube 0 00 * 01 * *

12 Q MMethod:CoverPIs Method: PIs : terms left without checkmarks. After identifying our PIs, we list them against the mintermsneeded to be covered m (0,1,2,3,5,7,13,15 ) 0 0 x x 0 x x 1 x 1 x Func

13 QMMethod:Covers Method To find a minimal cover, we first need to find essentialpis To do this we need to find columns that only haveone checkmark in them, the according row will thus show the essential PI. AfteridentifyingessentialPIs,thatare essential that are necessarily part of the cover, we cover any remaining mintermsusing a minimal set of PIs. In this example: F = A B +BD

14 QM Method: Another Example Tabular method to systematically find all prime implicants ƒ(a,b,c,d) BCD)= m(4,5,6,8,9,10,13) + d(0,7,15) Stage 1: Find all prime implicants Step 1: Fill Column 1 with ON set and DC set mintermindices. Group by number of 1's. Cube

15 Quine McCluskeyMethod Step 2:ApplyUnitingTheorem: Cube0 Cube1 Cube2 Compare elements of group x00 * w/ N 1's against those with N+1 1s. 1's 0100 x000 * Differ by one bit implies x adjacent x0 Eliminate variable and place in x * next column. E.g., 0000 vs yields x0 * 0000 vs yields x1 When used in a combination, mark with a check. If cannot be combined, mark with a star. These are the prime implicants. Repeat until no further combinations can be made x x x01 * x111 11x1

16 QuineMcluskeyMethod Step2:ApplyUnitingTheorem: Cube0 Cube1 Cube2 Compare elements of group x00 * 01xx * w/ N 1's against those with N+11's 1s x000 * x1x1 * Differ by one bit implies x adjacent x0 Eliminate variable and place in x * next column. E.g., 0000 vs yields x0 * 0000 vs yields x1 When used in a combination, mark with a check. If cannot be combined, mark with a star. These are the prime implicants. Repeat until no further combinations can be made x x x01 * x111 11x1

17 Finding the Minimum Cover We have so far found all the prime implicants 2 nd step of the Q M procedure is to find the smallest set of prime implicantsto coverthecompleteon complete on set setofthe the function

18 Finding the Minimum Cover This is accomplished through the prime implicant chart Columns are labeled with the mintermindices of the onset Rows are labeled with the mintermscovered byagivenprimeimplicant implicant Example a prime implicant ( 1 1) becomes minterms0101, 0111, 1101, 1111, which are indices of mintermsm5, m7, m13, m15

19 Coverage Table/ Chart 0,4(0 00) ( 000) 0,8( 000) 8,9(100 ) 8,10(10 0) 9,13(1 01) 4,5,6,7(01 ) 5,7,13,15( 1 1) Note: Don t include DCs in coverage table; they don t have covered by the final logic expression! rows = prime implicants columns = ON set elements placean""ifon setelementis an element is covered by the prime implicant

20 Coverage Table/ Chart 0,4(0 00) ( 000) 0,8( 000) 8,9(100 ) 8,10(10 0) 9,13(1 01) 4,5,6,7(01 ) 5,7,13,15( 1 1) rows = prime implicants columns = ON setelements elements place an "" if ON set element is covered by the prime implicant If column has a single, than the implicantassociated associated withthe the row is essential. It must appear in minimum cover

21 Coverage Table/ Chart: Eliminate 0,4(0 00) ( 000) 0,8( 000) 8,9(100 ) 8,10(10 0) 9,13(1 01) 4,5,6,7(01 ) 5,7,13,15( 1 1) rows = prime implicants columns = ON set elements place an "" if ON set element is covered by the prime implicant If column has a single il, than the implicantassociated with the row is essential. It must appear in minimum cover Eliminate all columns covered by essential primes

22 Coverage Table/ Chart: Eliminate 0,4(0 00) ( 000) 0,8( 000) 8,9(100 ) 8,10(10 0) 9,13(1 01) 4,5,6,7(01 ) 5,7,13,15( 1 1) rows = prime implicants columns = ON-set elements place an "" if ON-set element is covered by the prime implicant Find minimum set of rows that cover the remaining columns Eliminate all columns covered by essential primes

23 Coverage Table/ Chart: Eliminate 0,4(0 00) ( 000) 0,8( 000) 8,9(100 ) 8,10(10 0) 9,13(1 01) 4,5,6,7(01 ) 5,7,13,15( 1 1) If all are covered: Write the Implicants F= AB D + AC D + A B

24 Thanks 24

CS221: Digital Design. Dr. A. Sahu. Indian Institute of Technology Guwahati

CS221: Digital Design. Dr. A. Sahu. Indian Institute of Technology Guwahati CS221: Digital Design QMLogicMinimization Minimization Dr. A. Sahu DeptofComp.Sc.&Engg. Indian Institute of Technology Guwahati 1 Outline Study of Components Logic Implementation Using MUX & Decoder 4

More information

Quine-McCluskey (Tabular) Minimization

Quine-McCluskey (Tabular) Minimization Quine-McCluskey (Tabular) Minimization Two step process utilizing tabular listings to: Identify prime implicants (implicant tables) Identify minimal PI set (cover tables) All work is done in tabular form

More information

Principles of Computer Architecture. Appendix B: Reduction of Digital Logic. Chapter Contents

Principles of Computer Architecture. Appendix B: Reduction of Digital Logic. Chapter Contents B-1 Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix B: Reduction of Digital Logic B-2 Chapter Contents B.1 Reduction of Combinational Logic and Sequential Logic B.2 Reduction

More information

Digital Circuit And Logic Design I. Lecture 4

Digital Circuit And Logic Design I. Lecture 4 Digital Circuit And Logic Design I Lecture 4 Outline Combinational Logic Design Principles (2) 1. Combinational-circuit minimization 2. Karnaugh maps 3. Quine-McCluskey procedure Panupong Sornkhom, 2005/2

More information

DIGITAL ELECTRONICS & it0203 Semester 3

DIGITAL ELECTRONICS & it0203 Semester 3 DIGITAL ELECTRONICS & it0203 Semester 3 P.Rajasekar & C.M.T.Karthigeyan Asst.Professor SRM University, Kattankulathur School of Computing, Department of IT 8/22/2011 1 Disclaimer The contents of the slides

More information

Unit 6. Quine-McClusky Method. Unit 6 1

Unit 6. Quine-McClusky Method. Unit 6 1 Unit 6 Quine-McClusky Method Unit 6 1 Outline Determination of prime implicants The prime implicant chart Petrick s method Simplification of incompletely specified functions Unit 6 2 Overview (1/2) A systematic

More information

UNIT 5 KARNAUGH MAPS Spring 2011

UNIT 5 KARNAUGH MAPS Spring 2011 UNIT 5 KRNUGH MPS Spring 2 Karnaugh Maps 2 Contents Minimum forms of switching functions Two- and three-variable Four-variable Determination of minimum expressions using essential prime implicants Five-variable

More information

Lecture 6: Gate Level Minimization Syed M. Mahmud, Ph.D ECE Department Wayne State University

Lecture 6: Gate Level Minimization Syed M. Mahmud, Ph.D ECE Department Wayne State University Lecture 6: Gate Level Minimization Syed M. Mahmud, Ph.D ECE Department Wayne State University Original Source: Aby K George, ECE Department, Wayne State University Contents The Map method Two variable

More information

ELC224C. Karnaugh Maps

ELC224C. Karnaugh Maps KARNAUGH MAPS Function Simplification Algebraic Simplification Half Adder Introduction to K-maps How to use K-maps Converting to Minterms Form Prime Implicants and Essential Prime Implicants Example on

More information

CS221: Digital Design. Indian Institute of Technology Guwahati

CS221: Digital Design. Indian Institute of Technology Guwahati CS221: Digital Design KMap LogicMinimizationContd.. Minimization Dr. A. Sahu DeptofComp.Sc.&Engg. Indian Institute of Technology Guwahati 1 Outline Karnoughmap simplification 4 variable karnaughmap Don

More information

WEEK 3.1 MORE ON KARNAUGH MAPS

WEEK 3.1 MORE ON KARNAUGH MAPS WEEK 3. MORE ON KARNAUGH MAPS Don t Cares Sometimes, we might have inputs and it doesn t matter what the output is; i.e., we don t care what the output is. These situations are called don t cares. Rather

More information

Week-I. Combinational Logic & Circuits

Week-I. Combinational Logic & Circuits Week-I Combinational Logic & Circuits Overview Binary logic operations and gates Switching algebra Algebraic Minimization Standard forms Karnaugh Map Minimization Other logic operators IC families and

More information

K-map Definitions. abc

K-map Definitions. abc K-map efinitions b a bc Implicant ny single or any group of s is called an implicant of F. ny possible grouping of s is an implicant. b a Prime Implicant implicant that cannot be combined with some other

More information

Configurational Analysis beyond the Quine-McCluskeyMilan, algorithm 8 February / 29

Configurational Analysis beyond the Quine-McCluskeyMilan, algorithm 8 February / 29 Configurational Analysis beyond the Quine-McCluskey algorithm Adrian Dușa University of Bucharest Milan, 8 February 2018 Configurational Analysis beyond the Quine-McCluskeyMilan, algorithm 8 February 2018

More information

Chapter 4 Optimized Implementation of Logic Functions

Chapter 4 Optimized Implementation of Logic Functions Chapter 4 Optimized Implementation of Logic Functions Logic Minimization Karnaugh Maps Systematic Approach for Logic Minimization Minimization of Incompletely Specified Functions Tabular Method for Minimization

More information

CHAPTER 5 KARNAUGH MAPS

CHAPTER 5 KARNAUGH MAPS CHAPTER 5 1/36 KARNAUGH MAPS This chapter in the book includes: Objectives Study Guide 5.1 Minimum Forms of Switching Functions 5.2 Two- and Three-Variable Karnaugh Maps 5.3 Four-Variable Karnaugh Maps

More information

CHAPTER III BOOLEAN ALGEBRA

CHAPTER III BOOLEAN ALGEBRA CHAPTER III- CHAPTER III CHAPTER III R.M. Dansereau; v.. CHAPTER III-2 BOOLEAN VALUES INTRODUCTION BOOLEAN VALUES Boolean algebra is a form of algebra that deals with single digit binary values and variables.

More information

CSE 140: Components and Design Techniques for Digital Systems

CSE 140: Components and Design Techniques for Digital Systems Lecture 4: Four Input K-Maps CSE 4: Components and Design Techniques for Digital Systems CK Cheng Dept. of Computer Science and Engineering University of California, San Diego Outlines Boolean Algebra

More information

Lecture 4: Four Input K-Maps

Lecture 4: Four Input K-Maps Lecture 4: Four Input K-Maps CSE 4: Components and Design Techniques for Digital Systems Fall 24 CK Cheng Dept. of Computer Science and Engineering University of California, San Diego Outlines Boolean

More information

CMSC 313 Lecture 19 Combinational Logic Components Programmable Logic Arrays Karnaugh Maps

CMSC 313 Lecture 19 Combinational Logic Components Programmable Logic Arrays Karnaugh Maps CMSC 33 Lecture 9 Combinational Logic Components Programmable Logic rrays Karnaugh Maps UMC, CMSC33, Richard Chang Last Time & efore Returned midterm exam Half adders & full adders Ripple

More information

Simplification of Boolean Functions. Dept. of CSE, IEM, Kolkata

Simplification of Boolean Functions. Dept. of CSE, IEM, Kolkata Simplification of Boolean Functions Dept. of CSE, IEM, Kolkata 1 Simplification of Boolean Functions: An implementation of a Boolean Function requires the use of logic gates. A smaller number of gates,

More information

Contents. Chapter 3 Combinational Circuits Page 1 of 36

Contents. Chapter 3 Combinational Circuits Page 1 of 36 Chapter 3 Combinational Circuits Page of 36 Contents Combinational Circuits...2 3. Analysis of Combinational Circuits...3 3.. Using a Truth Table...3 3..2 Using a Boolean Function...6 3.2 Synthesis of

More information

Review. EECS Components and Design Techniques for Digital Systems. Lec 06 Minimizing Boolean Logic 9/ Review: Canonical Forms

Review. EECS Components and Design Techniques for Digital Systems. Lec 06 Minimizing Boolean Logic 9/ Review: Canonical Forms Review EECS 150 - Components and Design Techniques for Digital Systems Lec 06 Minimizing Boolean Logic 9/16-04 David Culler Electrical Engineering and Computer Sciences University of California, Berkeley

More information

CHAPTER III BOOLEAN ALGEBRA

CHAPTER III BOOLEAN ALGEBRA CHAPTER III- CHAPTER III CHAPTER III R.M. Dansereau; v.. CHAPTER III-2 BOOLEAN VALUES INTRODUCTION BOOLEAN VALUES Boolean algebra is a form of algebra that deals with single digit binary values and variables.

More information

ELEC Digital Logic Circuits Fall 2014 Logic Minimization (Chapter 3)

ELEC Digital Logic Circuits Fall 2014 Logic Minimization (Chapter 3) ELE 2200-002 Digital Logic ircuits Fall 204 Logic Minimization (hapter 3) Vishwani D. grawal James J. Danaher Professor Department of Electrical and omputer Engineering uburn University, uburn, L 36849

More information

DIGITAL TECHNICS I. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute 5. LECTURE: LOGIC SYNTHESIS

DIGITAL TECHNICS I. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute 5. LECTURE: LOGIC SYNTHESIS 202.0.5. DIGITL TECHNICS I Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 5. LECTURE: LOGIC SYNTHESIS st year BSc course st (utumn) term 202/203 5. LECTURE. Karnaugh map applications

More information

Outcomes. Spiral 1 / Unit 5. Logic Function Synthesis KARNAUGH MAPS. Karnaugh Maps

Outcomes. Spiral 1 / Unit 5. Logic Function Synthesis KARNAUGH MAPS. Karnaugh Maps -. -. Spiral / Unit Mark Redekopp Outcomes I know the difference between combinational and sequential logic and can name examples of each. I understand latency, throughput, and at least technique to improve

More information

Spiral 1 / Unit 5. Karnaugh Maps

Spiral 1 / Unit 5. Karnaugh Maps -. Spiral / Unit Karnaugh Maps -. Outcomes I know the difference between combinational and sequential logic and can name examples of each. I understand latency, throughput, and at least technique to improve

More information

Outcomes. Spiral 1 / Unit 5. Logic Function Synthesis KARNAUGH MAPS. Karnaugh Maps

Outcomes. Spiral 1 / Unit 5. Logic Function Synthesis KARNAUGH MAPS. Karnaugh Maps -. -. Spiral / Unit Mark Redekopp Outcomes I know the difference between combinational and sequential logic and can name examples of each. I understand latency, throughput, and at least technique to improve

More information

9.1. Unit 9. Implementing Combinational Functions with Karnaugh Maps or Memories

9.1. Unit 9. Implementing Combinational Functions with Karnaugh Maps or Memories . Unit Implementing Combinational Functions with Karnaugh Maps or Memories . Outcomes I can use Karnaugh maps to synthesize combinational functions with several outputs I can determine the appropriate

More information

CMSC 313 Lecture 19 Homework 4 Questions Combinational Logic Components Programmable Logic Arrays Introduction to Circuit Simplification

CMSC 313 Lecture 19 Homework 4 Questions Combinational Logic Components Programmable Logic Arrays Introduction to Circuit Simplification CMSC 33 Lecture 9 Homework 4 Questions Combinational Logic Components Programmable Logic rrays Introduction to Circuit Simplification UMC, CMSC33, Richard Chang CMSC 33, Computer Organization

More information

Fundamental Algorithms for System Modeling, Analysis, and Optimization

Fundamental Algorithms for System Modeling, Analysis, and Optimization Fundamental Algorithms for System Modeling, Analysis, and Optimization Edward A. Lee, Jaijeet Roychowdhury, Sanjit A. Seshia UC Berkeley EECS 244 Fall 2016 Lecturer: Yu-Yun Dai Copyright 2010-date, E.

More information

Chapter 2 Combinational Logic Circuits

Chapter 2 Combinational Logic Circuits Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Goal: To obtain the simplest implementation for a given function Optimization is a more formal

More information

The Karnaugh Map COE 202. Digital Logic Design. Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals

The Karnaugh Map COE 202. Digital Logic Design. Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals The Karnaugh Map COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals Presentation Outline Boolean Function Minimization The Karnaugh Map (K-Map) Two, Three,

More information

Optimizations and Tradeoffs. Combinational Logic Optimization

Optimizations and Tradeoffs. Combinational Logic Optimization Optimizations and Tradeoffs Combinational Logic Optimization Optimization & Tradeoffs Up to this point, we haven t really considered how to optimize our designs. Optimization is the process of transforming

More information

for Digital Systems Simplification of logic functions Tajana Simunic Rosing Sources: TSR, Katz, Boriello & Vahid

for Digital Systems Simplification of logic functions Tajana Simunic Rosing Sources: TSR, Katz, Boriello & Vahid SE140: omponents and Design Techniques for Digital Systems Simplification of logic functions Tajana Simunic Rosing 1 What we covered thus far: Number representations Where we are now inary, Octal, Hex,

More information

E&CE 223 Digital Circuits & Systems. Lecture Transparencies (Boolean Algebra & Logic Gates) M. Sachdev

E&CE 223 Digital Circuits & Systems. Lecture Transparencies (Boolean Algebra & Logic Gates) M. Sachdev E&CE 223 Digital Circuits & Systems Lecture Transparencies (Boolean Algebra & Logic Gates) M. Sachdev 4 of 92 Section 2: Boolean Algebra & Logic Gates Major topics Boolean algebra NAND & NOR gates Boolean

More information

Logic Synthesis and Verification

Logic Synthesis and Verification Logic Synthesis and Verification Jie-Hong Roland Jiang 江介宏 Department of Electrical Engineering National Taiwan University Fall 24 Two-Level Logic Minimization (/2) Reading: Logic Synthesis in a Nutshell

More information

CS/EE 181a 2008/09 Lecture 4

CS/EE 181a 2008/09 Lecture 4 CS/EE 181a 28/9 Lecture 4 General topic of today s lecture: Logic Optimization Karnaugh maps. Quine-McCluskey tabulation method (not in detail). Non series-parallel networks (some care is required). Reference

More information

Working with Combinational Logic. Design example: 2x2-bit multiplier

Working with Combinational Logic. Design example: 2x2-bit multiplier Working with ombinational Logic Simplification two-level simplification exploiting don t cares algorithm for simplification Logic realization two-level logic and canonical forms realized with NNs and NORs

More information

E&CE 223 Digital Circuits & Systems. Lecture Transparencies (Boolean Algebra & Logic Gates) M. Sachdev. Section 2: Boolean Algebra & Logic Gates

E&CE 223 Digital Circuits & Systems. Lecture Transparencies (Boolean Algebra & Logic Gates) M. Sachdev. Section 2: Boolean Algebra & Logic Gates Digital Circuits & Systems Lecture Transparencies (Boolean lgebra & Logic Gates) M. Sachdev 4 of 92 Section 2: Boolean lgebra & Logic Gates Major topics Boolean algebra NND & NOR gates Boolean algebra

More information

Chapter 4. Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. elements. Dr.

Chapter 4. Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. elements. Dr. Chapter 4 Dr. Panos Nasiopoulos Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. Sequential: In addition, they include storage elements Combinational

More information

L6: Two-level minimization. Reading material

L6: Two-level minimization. Reading material L6: Two-level minimization Reading material de Micheli pp. 269-343 p. 2 - Advanced Logic Design L6 - Elena Dubrova Formulation of the two-level minimization problem input: a Boolean function f(x,x 2,...,x

More information

Karnaugh Maps Objectives

Karnaugh Maps Objectives Karnaugh Maps Objectives For Karnaugh Maps of up to 5 variables Plot a function from algebraic, minterm or maxterm form Obtain minimum Sum of Products and Product of Sums Understand the relationship between

More information

ESE535: Electronic Design Automation. Today. Problem. EDA Use PLA. Programmable Array Logic (PLAs) Two-Level Logic Optimization

ESE535: Electronic Design Automation. Today. Problem. EDA Use PLA. Programmable Array Logic (PLAs) Two-Level Logic Optimization ESE535: Electronic Design Automation Today Day 4: February 25, 2009 Two-Level Logic-Synthesis Two-Level Logic Optimization Problem Definitions Basic Algorithm: Quine-McClusky Improvements 1 2 Problem EDA

More information

Midterm1 Review. Jan 24 Armita

Midterm1 Review. Jan 24 Armita Midterm1 Review Jan 24 Armita Outline Boolean Algebra Axioms closure, Identity elements, complements, commutativity, distributivity theorems Associativity, Duality, De Morgan, Consensus theorem Shannon

More information

Digital Logic Circuits - Switching Algebra - Combinational Circuits -

Digital Logic Circuits - Switching Algebra - Combinational Circuits - Digital Logic Circuits - Switching Algebra - Combinational Circuits - Dr. Voicu Groza SITE Hall, Room 57 562 58 ext. 259 Groza@EECS.uOttawa.ca Outline Logic Functions Boolean Algebra Logic Functions Minimization

More information

Gate-Level Minimization

Gate-Level Minimization Gate-Level Minimization Dr. Bassem A. Abdullah Computer and Systems Department Lectures Prepared by Dr.Mona Safar, Edited and Lectured by Dr.Bassem A. Abdullah Outline 1. The Map Method 2. Four-variable

More information

Exact and heuristic minimization of Boolean functions

Exact and heuristic minimization of Boolean functions Eact and heuristic minimization of Boolean functions Quine a McCluskey Method a) Generation of all prime implicants b) Selection of a minimum subset of prime implicants, which will represent the original

More information

COMBINATIONAL LOGIC FUNCTIONS

COMBINATIONAL LOGIC FUNCTIONS COMBINATIONAL LOGIC FUNCTIONS Digital logic circuits can be classified as either combinational or sequential circuits. A combinational circuit is one where the output at any time depends only on the present

More information

Systems I: Computer Organization and Architecture

Systems I: Computer Organization and Architecture Systems I: Computer Organization and Architecture Lecture 6 - Combinational Logic Introduction A combinational circuit consists of input variables, logic gates, and output variables. The logic gates accept

More information

ELEC Digital Logic Circuits Fall 2015 Logic Minimization (Chapter 3)

ELEC Digital Logic Circuits Fall 2015 Logic Minimization (Chapter 3) ELE 2200-002 igital Logic ircuits Fall 205 Logic Minimization (hapter 3) Vishwani. grawal James J. anaher Professor epartment of Electrical and omputer Engineering uburn University, uburn, L 36849 http://www.eng.auburn.edu/~vagrawal

More information

Review for Test 1 : Ch1 5

Review for Test 1 : Ch1 5 Review for Test 1 : Ch1 5 October 5, 2006 Typeset by FoilTEX Positional Numbers 527.46 10 = (5 10 2 )+(2 10 1 )+(7 10 0 )+(4 10 1 )+(6 10 2 ) 527.46 8 = (5 8 2 ) + (2 8 1 ) + (7 8 0 ) + (4 8 1 ) + (6 8

More information

CS/EE 181a 2010/11 Lecture 4

CS/EE 181a 2010/11 Lecture 4 CS/EE 181a 21/11 Lecture 4 General topic of today s lecture: Logic Optimization Karnaugh maps. Quine-McCluskey tabulation method (not in detail). Non series-parallel networks (some care is required). Reference

More information

( c) Give logic symbol, Truth table and circuit diagram for a clocked SR flip-flop. A combinational circuit is defined by the function

( c) Give logic symbol, Truth table and circuit diagram for a clocked SR flip-flop. A combinational circuit is defined by the function Question Paper Digital Electronics (EE-204-F) MDU Examination May 2015 1. (a) represent (32)10 in (i) BCD 8421 code (ii) Excess-3 code (iii) ASCII code (b) Design half adder using only NAND gates. ( c)

More information

Review for B33DV2-Digital Design. Digital Design

Review for B33DV2-Digital Design. Digital Design Review for B33DV2 The Elements of Modern Behaviours Design Representations Blocks Waveforms Gates Truth Tables Boolean Algebra Switches Rapid Prototyping Technologies Circuit Technologies TTL MOS Simulation

More information

Unit 2 Session - 6 Combinational Logic Circuits

Unit 2 Session - 6 Combinational Logic Circuits Objectives Unit 2 Session - 6 Combinational Logic Circuits Draw 3- variable and 4- variable Karnaugh maps and use them to simplify Boolean expressions Understand don t Care Conditions Use the Product-of-Sums

More information

EECS150 - Digital Design Lecture 19 - Combinational Logic Circuits : A Deep Dive

EECS150 - Digital Design Lecture 19 - Combinational Logic Circuits : A Deep Dive EECS150 - Digital Design Lecture 19 - Combinational Logic Circuits : A Deep Dive March 30, 2010 John Wawrzynek Spring 2010 EECS150 - Lec19-cl1 Page 1 Boolean Algebra I (Representations of Combinational

More information

Logic. Combinational. inputs. outputs. the result. system can

Logic. Combinational. inputs. outputs. the result. system can Digital Electronics Combinational Logic Functions Digital logic circuits can be classified as either combinational or sequential circuits. A combinational circuit is one where the output at any time depends

More information

Introduction to Digital Logic Missouri S&T University CPE 2210 Karnaugh Maps

Introduction to Digital Logic Missouri S&T University CPE 2210 Karnaugh Maps Introduction to Digital Logic Missouri S&T University CPE 2210 Karnaugh Maps Egemen K. Çetinkaya Egemen K. Çetinkaya Department of Electrical & Computer Engineering Missouri University of Science and Technology

More information

Logical Design of Digital Systems

Logical Design of Digital Systems Lecture 4 Table of Content 1. Combinational circuit design 2. Elementary combinatorial circuits for data transmission 3. Memory structures 4. Programmable logic devices 5. Algorithmic minimization approaches

More information

CSE140: Components and Design Techniques for Digital Systems. Logic minimization algorithm summary. Instructor: Mohsen Imani UC San Diego

CSE140: Components and Design Techniques for Digital Systems. Logic minimization algorithm summary. Instructor: Mohsen Imani UC San Diego CSE4: Components and Design Techniques for Digital Systems Logic minimization algorithm summary Instructor: Mohsen Imani UC San Diego Slides from: Prof.Tajana Simunic Rosing & Dr.Pietro Mercati Definition

More information

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700: Digital Logic Design Winter Notes - Unit 2

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700: Digital Logic Design Winter Notes - Unit 2 ECE-7: Digital Logic Design Winter 8 Notes - Unit OPTIMIZED IMPLEMENTATION OF LOGIC FUNCTIONS BASIC TECHNIQUES: We can alas minimie logic unctions using the Boolean theorems. Hoever, more poerul methods

More information

Logic Design I (17.341) Fall Lecture Outline

Logic Design I (17.341) Fall Lecture Outline Logic Design I (17.341) Fall 2011 Lecture Outline Class # 06 October 24, 2011 Dohn Bowden 1 Today s Lecture Administrative Main Logic Topic Homework 2 Course Admin 3 Administrative Admin for tonight Syllabus

More information

Logic Minimization. Two-Level. University of California. Prof. Srinivas Devadas. Prof. Richard Newton Prof. Sanjit Seshia. Prof.

Logic Minimization. Two-Level. University of California. Prof. Srinivas Devadas. Prof. Richard Newton Prof. Sanjit Seshia. Prof. Two-Level Logic Minimization Prof. Srinivas Devadas MIT Prof. Kurt Keutzer Prof. Richard Newton Prof. Sanjit Seshia University of California Berkeley, CA 1 Topics Motivation Boolean functions & notation

More information

Total Time = 90 Minutes, Total Marks = 50. Total /50 /10 /18

Total Time = 90 Minutes, Total Marks = 50. Total /50 /10 /18 University of Waterloo Department of Electrical & Computer Engineering E&CE 223 Digital Circuits and Systems Midterm Examination Instructor: M. Sachdev October 23rd, 2007 Total Time = 90 Minutes, Total

More information

PI = { a.b.c, ac d, b cd, ab d, bd} cd

PI = { a.b.c, ac d, b cd, ab d, bd} cd Digital Logic Design: Principles and Practices ELG5195 (EACJ5705 ), Carleton CRN: 18371 Assignment #1 Question 1: a) Using iterated consensus find all the prime implicants of the following function: F(

More information

14:332:231 DIGITAL LOGIC DESIGN

14:332:231 DIGITAL LOGIC DESIGN :: DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University Electrical & Computer Engineering Fall Lecture #: Combinational Circuit Synthesis II hat if we have input variables? V = V = of Example with variables

More information

Lecture 6: Manipulation of Algebraic Functions, Boolean Algebra, Karnaugh Maps

Lecture 6: Manipulation of Algebraic Functions, Boolean Algebra, Karnaugh Maps EE210: Switching Systems Lecture 6: Manipulation of Algebraic Functions, Boolean Algebra, Karnaugh Maps Prof. YingLi Tian Feb. 21/26, 2019 Department of Electrical Engineering The City College of New York

More information

(Boolean Algebra, combinational circuits) (Binary Codes and -arithmetics)

(Boolean Algebra, combinational circuits) (Binary Codes and -arithmetics) Task 1. Exercises: Logical Design of Digital Systems Seite: 1 Self Study (Boolean Algebra, combinational circuits) 1.1 Minimize the function f 1 a ab ab by the help of Boolean algebra and give an implementation

More information

CS470: Computer Architecture. AMD Quad Core

CS470: Computer Architecture. AMD Quad Core CS470: Computer Architecture Yashwant K. Malaiya, Professor malaiya@cs.colostate.edu AMD Quad Core 1 Architecture Layers Building blocks Gates, flip-flops Functional bocks: Combinational, Sequential Instruction

More information

Combinational Logic Fundamentals

Combinational Logic Fundamentals Topic 3: Combinational Logic Fundamentals In this note we will study combinational logic, which is the part of digital logic that uses Boolean algebra. All the concepts presented in combinational logic

More information

Ch 2. Combinational Logic. II - Combinational Logic Contemporary Logic Design 1

Ch 2. Combinational Logic. II - Combinational Logic Contemporary Logic Design 1 Ch 2. Combinational Logic II - Combinational Logic Contemporary Logic Design 1 Combinational logic Define The kind of digital system whose output behavior depends only on the current inputs memoryless:

More information

Lecture 7: Karnaugh Map, Don t Cares

Lecture 7: Karnaugh Map, Don t Cares EE210: Switching Systems Lecture 7: Karnaugh Map, Don t Cares Prof. YingLi Tian Feb. 28, 2019 Department of Electrical Engineering The City College of New York The City University of New York (CUNY) 1

More information

Simplifying Logic Circuits with Karnaugh Maps

Simplifying Logic Circuits with Karnaugh Maps Simplifying Logic Circuits with Karnaugh Maps The circuit at the top right is the logic equivalent of the Boolean expression: f = abc + abc + abc Now, as we have seen, this expression can be simplified

More information

CDA 3200 Digital Systems. Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012

CDA 3200 Digital Systems. Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012 CDA 3200 Digital Systems Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012 Outline Combinational Logic Design Using a Truth Table Minterm and Maxterm Expansions General Minterm and

More information

CHAPTER 12 Boolean Algebra

CHAPTER 12 Boolean Algebra 318 Chapter 12 Boolean Algebra CHAPTER 12 Boolean Algebra SECTION 12.1 Boolean Functions 2. a) Since x 1 = x, the only solution is x = 0. b) Since 0 + 0 = 0 and 1 + 1 = 1, the only solution is x = 0. c)

More information

Karnaugh Maps ف ر آ ا د : ا ا ب ا م آ ه ا ن ر ا

Karnaugh Maps ف ر آ ا د : ا ا ب ا م آ ه ا ن ر ا Karnaugh Maps مخطط آارنوف اعداد:محمد اسماعيل آلية علوم الحاسوب جامعة امدرمان الاهلية الاهداء الي آل من يسلك طريق العلم والمعرفة في هذا المجال Venn Diagrams Venn diagram to represent the space of minterms.

More information

Boolean cubes EECS150. Mapping truth tables onto cubes. Simplification. The Uniting Theorem. Three variable example

Boolean cubes EECS150. Mapping truth tables onto cubes. Simplification. The Uniting Theorem. Three variable example EES5 Section 5 Simplification and State Minimization Fall 2 -cube X oolean cubes Visual technique for indentifying when the uniting theorem can be applied n input variables = n-dimensional "cube" Y 2-cube

More information

Minimization techniques

Minimization techniques Pune Vidyarthi Griha s COLLEGE OF ENGINEERING, NSIK - 4 Minimization techniques By Prof. nand N. Gharu ssistant Professor Computer Department Combinational Logic Circuits Introduction Standard representation

More information

Binary logic consists of binary variables and logical operations. The variables are

Binary logic consists of binary variables and logical operations. The variables are 1) Define binary logic? Binary logic consists of binary variables and logical operations. The variables are designated by the alphabets such as A, B, C, x, y, z, etc., with each variable having only two

More information

15.1 Elimination of Redundant States

15.1 Elimination of Redundant States 15.1 Elimination of Redundant States In Ch. 14 we tried not to have unnecessary states What if we have extra states in the state graph/table? Complete the table then eliminate the redundant states Chapter

More information

Chapter 2 Combinational Logic Circuits

Chapter 2 Combinational Logic Circuits Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 1 Gate Circuits and Boolean Equations Charles Kime & Thomas Kaminski 2008 Pearson Education, Inc. Overview Part 1 Gate

More information

3. PRINCIPLES OF COMBINATIONAL LOGIC

3. PRINCIPLES OF COMBINATIONAL LOGIC Principle of ombinational Logic -. PRINIPLES OF OMINTIONL LOGI Objectives. Understand the design & analysis procedure of combinational logic.. Understand the optimization of combinational logic.. efinitions

More information

CS221: Digital Design Data Path Components Adder

CS221: Digital Design Data Path Components Adder CS221: Digital Design Data Path Coponents Adder Dr. A. Sahu DeptofCop.Sc.&Engg. Indian Institute of Technology Guwahati Outline Adder: Basic Model Carry Propagation and Generation MachesterAdder Carry

More information

Chapter 2 Combinational Logic Circuits

Chapter 2 Combinational Logic Circuits Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Charles Kime & Thomas Kaminski 2004 Pearson Education, Inc. Terms of Use (Hyperlinks are active

More information

CMSC 313 Preview Slides

CMSC 313 Preview Slides CMSC 33 Preview Slies These are raft slies. The actual slies presente in lecture may be ifferent ue to last minute changes, scheule slippage,... UMBC, CMSC33, Richar Chang CMSC 33 Lecture

More information

Digital Design for Multiplication

Digital Design for Multiplication Digital Design for Multiplication Norman Matloff October 15, 2003 c 2003, N.S. Matloff 1 Overview A cottage industry exists in developing fast digital logic to perform arithmetic computations. Fast addition,

More information

L2: Combinational Logic Design (Construction and Boolean Algebra)

L2: Combinational Logic Design (Construction and Boolean Algebra) L2: Combinational Logic Design (Construction and oolean lgebra) cknowledgements: Materials in this lecture are courtesy of the following people and used with permission. - Randy H. Katz (University of

More information

ENG2410 Digital Design Combinational Logic Circuits

ENG2410 Digital Design Combinational Logic Circuits ENG240 Digital Design Combinational Logic Circuits Fall 207 S. Areibi School of Engineering University of Guelph Binary variables Binary Logic Can be 0 or (T or F, low or high) Variables named with single

More information

CS221: Digital Design. Dr. A. Sahu. Indian Institute of Technology Guwahati

CS221: Digital Design. Dr. A. Sahu. Indian Institute of Technology Guwahati CS221: Digital Design Counter&Registers Dr. A. Sahu DeptofComp.Sc.&Engg. Indian Institute of Technology Guwahati Outline Counter : Synchronous Vs Asynchronous Counter: Finite it State t Machine Mhi A register

More information

DO NOT COPY DO NOT COPY

DO NOT COPY DO NOT COPY Drill Problems 3 benches. Another practical book is VHDL for Programmable Logic, by Kevin Skahill of Cypress Semiconductor (Addison-esley, 1996). All of the ABEL and VHDL examples in this chapter and throughout

More information

COM111 Introduction to Computer Engineering (Fall ) NOTES 6 -- page 1 of 12

COM111 Introduction to Computer Engineering (Fall ) NOTES 6 -- page 1 of 12 COM111 Introduction to Computer Engineering (Fall 2006-2007) NOTES 6 -- page 1 of 12 Karnaugh Maps In this lecture, we will discuss Karnaugh maps (K-maps) more formally than last time and discuss a more

More information

Lecture 22 Chapters 3 Logic Circuits Part 1

Lecture 22 Chapters 3 Logic Circuits Part 1 Lecture 22 Chapters 3 Logic Circuits Part 1 LC-3 Data Path Revisited How are the components Seen here implemented? 5-2 Computing Layers Problems Algorithms Language Instruction Set Architecture Microarchitecture

More information

Chapter 2. Digital Logic Basics

Chapter 2. Digital Logic Basics Chapter 2 Digital Logic Basics 1 2 Chapter 2 2 1 Implementation using NND gates: We can write the XOR logical expression B + B using double negation as B+ B = B+B = B B From this logical expression, we

More information

UNIT II COMBINATIONAL CIRCUITS:

UNIT II COMBINATIONAL CIRCUITS: UNIT II COMBINATIONAL CIRCUITS: INTRODUCTION: The digital system consists of two types of circuits, namely (i) (ii) Combinational circuits Sequential circuits Combinational circuit consists of logic gates

More information

XI STANDARD [ COMPUTER SCIENCE ] 5 MARKS STUDY MATERIAL.

XI STANDARD [ COMPUTER SCIENCE ] 5 MARKS STUDY MATERIAL. 2017-18 XI STANDARD [ COMPUTER SCIENCE ] 5 MARKS STUDY MATERIAL HALF ADDER 1. The circuit that performs addition within the Arithmetic and Logic Unit of the CPU are called adders. 2. A unit that adds two

More information

UNIT 4 MINTERM AND MAXTERM EXPANSIONS

UNIT 4 MINTERM AND MAXTERM EXPANSIONS UNIT 4 MINTERM AND MAXTERM EXPANSIONS Spring 2 Minterm and Maxterm Expansions 2 Contents Conversion of English sentences to Boolean equations Combinational logic design using a truth table Minterm and

More information

L2: Combinational Logic Design (Construction and Boolean Algebra)

L2: Combinational Logic Design (Construction and Boolean Algebra) L2: Combinational Logic Design (Construction and Boolean Algebra) Acknowledgements: Lecture material adapted from Chapter 2 of R. Katz, G. Borriello, Contemporary Logic Design (second edition), Pearson

More information

Heuristic Minimization of Two Level Circuits

Heuristic Minimization of Two Level Circuits Heuristic Minimization of Two Level Circuits Sungho Kang Yonsei University Outline Local Search Checking for Equivalence and Tautology Choosing the Right Direction Identifying Essential Implicants 2 Local

More information