Minimization techniques

Size: px
Start display at page:

Download "Minimization techniques"

Transcription

1 Pune Vidyarthi Griha s COLLEGE OF ENGINEERING, NSIK - 4 Minimization techniques By Prof. nand N. Gharu ssistant Professor Computer Department

2 Combinational Logic Circuits Introduction Standard representation of canonical forms (SOP & POS), Maxterm and Minterm, Conversion between SOP and POS forms K-map reduction techniques upto 4 variables (SOP & POS form), Design of Half dder, Full dder, Half Subtractor & Full Subtractor using k-map Code Converter using K-map: Gray to Binary Binary to Gray Code Converter (upto 4 bit) IC 7447 as BCD to 7- Segment decoder driver IC 7483 as dder & Subtractor, 1 Digit BCD dder Block Schematic of LU IC IC /29/2017 2

3 Standard Representation ny logical expression can be expressed in the following two forms: Sum of Product (SOP) Form Product of Sum (POS) Form 8/29/2017 3

4 SOP Form For Example, logical expression given is; Sum Y. B B. C C. Product 8/29/2017 4

5 POS Form For Example, logical expression given is; Product Y ( B).( B C).( C) Sum 8/29/2017 5

6 Standard or Canonical SOP & POS Forms We can say that a logic expression is said to be in the standard (or canonical) SOP or POS form if each product term (for SOP) and sum term (for POS) consists of all the literals in their complemented or uncomplemented form. 8/29/2017 6

7 Standard SOP Y C C C Each product term consists all the literals 8/29/2017 7

8 Standard POS Y ( B C).( B C).( B C) Each sum term consists all the literals 8/29/2017 8

9 Examples Sr. No. Expression Type 1 Non Standard SOP Y C C 2 Standard SOP Y 3 Standard POS Y ( B).( B).( B) 4 Non Standard POS Y ( B).( B C) 8/29/2017 9

10 Conversion of SOP form to Standard SOP Procedure: 1. Write down all the terms. 2. If one or more variables are missing in any product term, expand the term by multiplying it with the sum of each one of the missing variable and its complement. 3. Drop out the redundant terms 8/29/

11 Example 1 Convert given expression into its standard SOP form Y C BC Y C BC Missing literal is C Missing literal is B Missing literal is Y.( C C) C.( B B) BC.( ) Term formed by ORing of missing literal & its complement 8/29/

12 Example 1 Continue. Y.( C C) C.( B B) BC.( ) Y C C C C C C Y C C C C C C Y C C C C Standard SOP form Each product term consists all the literals 8/29/

13 Conversion of POS form to Standard POS Procedure: 1. Write down all the terms. 2. If one or more variables are missing in any sum term, expand the term by adding the products of each one of the missing variable and its complement. 3. Drop out the redundant terms 8/29/

14 Example 2 Convert given expression into its standard SOP form Y ( B).( C) ( B C) Y ( B).( C) ( B C) Missing literal is C Missing literal is B Missing literal is Y ( B CC).( C BB).( B C ) Term formed by NDing of missing literal & its complement 8/29/

15 Example 2 Continue. Y ( B CC).( C BB).( B C ) Y ( B C)( B C).( B C)( B C).( B C)( B C) Y ( B C)( B C)( B C)( B C) Y ( B C)( B C)( B C)( B C) Standard POS form Each sum term consists all the literals 8/29/

16 Concept of Minterm and Maxterm Minterm: Each individual term in the standard SOP form is called as Minterm. Maxterm: Each individual term in the standard POS form is called as Maxterm. 8/29/

17 The concept of minterm and max term allows us to introduce a very convenient shorthand notation to express logic functions 8/29/

18 Minterms & Maxterms for 3 variable/literal logic function Variables Minterms Maxterms B C mi Mi C m0 C m1 C m2 C m3 C m4 C m5 C m6 C m7 B C M 0 B C M 1 B C M 2 B C M 3 B C M 4 B C M 5 B C M 6 B C M 7 8/29/2017 mit Nevase 18

19 Minterms and maxterms Each minterm is represented by m i where i=0,1,2,3,.,2 n-1 Each maxterm is represented by M i where i=0,1,2,3,.,2 n-1 If n number of variables forms the function, then number of minterms or maxterms will be 2 n i.e. for 3 variables function f(,b,c), the number of minterms or maxterms are 2 3 =8 8/29/

20 Minterms & Maxterms for 2 variable/literal logic function Variables Minterms Maxterms B mi Mi 0 0 m0 B M m1 m2 B M 1 B M 2 B M m3 3 8/29/

21 Representation of Logical expression using minterm Y C C C C m 7 m 3 m 4 m 5 Y m7 m3 m4 m5 Logical Expression Corresponding minterms Y m(3,4,5,7) OR Y f (, B, C) m(3,4,5,7) where denotes sum of products 8/29/

22 Representation of Logical expression using maxterm Y ( B C).( B C).( B C) M 2 M 0 M 6 Logical Expression Corresponding maxterms Y M. M. M Y M(0,2,6) OR Y f (, B, C) M (0,2,6) where denotes product of sum 8/29/

23 Conversion from SOP to POS & Vice versa The relationship between the expressions using minters and maxterms is complementary. We can exploit this complementary relationship to write the expressions in terms of maxterms if the expression in terms of minterms is known and vice versa 8/29/

24 Conversion from SOP to POS & Vice versa For example, if a SOP expression for 4 variable is given by, Y m(0,1, 3, 5, 6, 7,11,12,15) Then we can get the equivalent POS expression using the complementary relationship as follows, Y M(2, 4,8, 9,10,13,14) 8/29/

25 Examples 1. Convert the given expression into standard form Y BC C 2. Convert the given expression into standard form Y ( B).( C) 8/29/

26 Combinational Logic Circuits Introduction Standard representation of canonical forms (SOP & POS), Maxterm and Minterm, Conversion between SOP and POS forms K-map reduction techniques upto 4 variables (SOP & POS form), Design of Half dder, Full dder, Half Subtractor & Full Subtractor using k-map Code Converter using K-map: Gray to Binary, Binary to Gray Code Converter (upto 4 bit) IC 7447 as BCD to 7- Segment decoder driver IC 7483 as dder & Subtractor, 1 Digit BCD dder Block Schematic of LU IC IC /29/

27 Karnaugh Map (K-map) In the algebraic method of simplification, we need to write lengthy equations, find the common terms, manipulate the expressions etc., so it is time consuming work. Thus K-map is another simplification technique to reduce the Boolean equation. 8/29/

28 Karnaugh Map (K-map) It overcomes all the disadvantages of algebraic simplification techniques. The information contained in a truth table or available in the SOP or POS form is represented on K-map. 8/29/

29 Karnaugh Map (K-map) K-map Structure - 2 Variable & B are variables or inputs 0 & 1 are values of & B 2 variable k-map consists of 4 boxes i.e. 2 2 =4 B /29/

30 Karnaugh Map (K-map) K-map Structure - 2 Variable Inside 4 boxes we have enter values of Y i.e. output B B B B m0 m1 m2 m3 K-map & its associated minterms 8/29/

31 Karnaugh Map (K-map) Relationship between Truth Table & K-map B Y B B B B B B /29/

32 C Karnaugh Map (K-map) K-map Structure - 3 Variable, B & C are variables or inputs variable k-map consists of 8 boxes i.e. 2 3 =8 BC BC /29/

33 C Karnaugh Map (K-map) 3 Variable K-map & its associated product terms 0 1 BC C C C C C C C C C C C C BC C C C C C C C C 1 C C C C 8/29/

34 Karnaugh Map (K-map) 3 Variable K-map & its associated minterms C 0 1 BC m0 m2 m1 m3 m6 m7 m4 m BC m0 m4 m1 m5 m3 m7 0 m0 m1 m3 m2 10 m2 m6 1 m4 m5 m7 m6 8/29/

35 Karnaugh Map (K-map) K-map Structure - 4 Variable, B, C & D are variables or inputs 4 variable k-map consists of 16 boxes i.e. 2 4 =16 CD CD /29/

36 Karnaugh Map (K-map) 4 Variable K-map and its associated product terms CD CD CD CD CD CD 00 CD CD CD CD 01 CD CD CD CD 01 CD CD CD CD 11 CD CD CD CD 11 CD CD CD CD 10 CD CD CD CD 10 CD CD CD CD 8/29/

37 Karnaugh Map (K-map) 4 Variable K-map and its associated minterms CD CD m 0 m 4 m 12 m 8 00 m 0 m 1 m 3 m 2 01 m 1 m 5 m 13 m 9 01 m 4 m 5 m 7 m 6 11 m 3 m 7 m 15 m m 12 m 13 m 15 m m 2 m 6 m 11 m m 8 m 9 m 11 m 10 8/29/

38 Representation of Standard SOP form expression on K-map For example, SOP equation is given as Y C C C C C The given expression is in the standard SOP form. Each term represents a minterm. We have to enter 1 in the boxes corresponding to each minterm as below C C BC BC BC BC BC C C C 8/29/

39 Simplification of K-map Once we plot the logic function or truth table on K-map, we have to use the grouping technique for simplifying the logic function. Grouping means the combining the terms in adjacent cells. The grouping of either 1 s or 0 s results in the simplification of boolean expression. 8/29/

40 Simplification of K-map If we group the adjacent 1 s then the result of simplification is SOP form If we group the adjacent 0 s then the result of simplification is POS form 8/29/

41 Grouping While grouping, we should group most number of 1 s. The grouping follows the binary rule i.e we can group 1,2,4,8,16,32,.. number of 1 s. We cannot group 3,5,7, number of 1 s Pair: group of two adjacent 1 s is called as Pair Quad: group of four adjacent 1 s is called as Quad Octet: group of eight adjacent 1 s is called as Octet 8/29/

42 Grouping of Two djacent 1 s : Pair pair eliminates 1 variable C C BC BC BC BC BC Y C C Y ( C C) Y ( C C 1) 8/29/

43 Grouping of Two djacent 1 s : Pair BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC B B 0 B /29/

44 Grouping of Two djacent 1 s : Pair CD CD CD CD CD /29/

45 Possible Grouping of Four djacent 1 s : Quad Quad eliminates 2 variable CD CD CD CD CD CD CD CD CD CD /29/

46 Possible Grouping of Four djacent 1 s : Quad Quad eliminates 2 variable CD CD CD CD CD CD CD CD CD CD /29/

47 Possible Grouping of Four djacent 1 s : Quad Quad eliminates 2 variable CD CD CD CD CD CD CD CD CD CD /29/

48 Possible Grouping of Four djacent 1 s : Quad Quad eliminates 2 variable CD CD CD CD CD CD CD CD CD CD /29/

49 Possible Grouping of Eight djacent 1 s : Octet Octet eliminates 3 variable CD CD CD CD CD CD CD CD CD CD /29/

50 Possible Grouping of Eight djacent 1 s : Octet Octet eliminates 3 variable CD CD CD CD CD CD CD CD CD CD /29/

51 Rules for K-map simplification 1. Groups may not include any cell containing a zero. B B B B B B Not ccepted ccepted 8/29/

52 Rules for K-map simplification 2. Groups may be horizontal or vertical, but may not be diagonal B B B B B B Not ccepted ccepted 8/29/

53 Rules for K-map simplification 3. Groups must contain 1,2,4,8 or in general 2 n cells BC BC BC BC BC BC BC BC BC BC B B B B B B Not ccepted ccepted 8/29/

54 Rules for K-map simplification 4. Each group should be as large as possible BC BC 00 BC 01 BC 11 BC BC BC 00 BC 01 BC 11 BC Not ccepted ccepted 8/29/

55 Rules for K-map simplification 5. Each cell containing a one must be in at least one group BC BC BC BC BC /29/

56 Rules for K-map simplification 6. Groups may be overlap BC BC BC BC BC /29/

57 Rules for K-map simplification 7. Groups may wrap around the table. The leftmost cell in a row may be grouped with rightmost cell and the top cell in a column may be grouped with bottom cell CD CD CD CD CD BC BC BC BC BC /29/

58 Rules for K-map simplification 8. There should be as few groups as possible, as long as this does not contradict any of the previous rules. BC BC 00 BC 01 BC 11 BC BC BC 00 BC 01 BC 11 BC Not ccepted ccepted 8/29/

59 Rules for K-map simplification 9. pair eliminates one variable. 10. Quad eliminates two variables. 11. octet eliminates three variables 8/29/

60 Example 1 For the given K-map write simplified Boolean expression C C C /29/

61 Example 1 continue.. C C C C BC Simplified Boolean expression Y BC C 8/29/

62 Example 2 For the given K-map write simplified Boolean expression C C C /29/

63 Example 2 continue.. C C C C Simplified Boolean expression Y B C B 8/29/

64 Example 3 logical expression in the standard SOP form is as follows; Y C C C C Minimize it with using the K-map technique 8/29/

65 Example 3 continue Y C C C C BC BC 00 BC 01 BC 11 BC C Simplified Boolean expression C Y C C 8/29/

66 Example 4 logical expression representing a logic circuit is; Y m(0,1, 2, 5,13,15) Draw the K-map and find the minimized logical expression 8/29/

67 Example 4 continue.. Y m(0,1, 2, 5,13,15) CD CD CD CD CD Simplified Boolean expression D Y D CD D CD D 8/29/

68 Example 5 Minimize the following Boolean expression using K-map ; f (, B, C, D) m(1,3,5,9,11,13) 8/29/

69 Example 5 continue.. f (, B, C, D) m(1,3,5,9,11,13) CD CD CD CD CD Simplified Boolean expression f BD CD BD CD f D( B C) 8/29/

70 Example 6 Minimize the following Boolean expression using K-map ; f (, B, C, D) m(4,5,8,9,11,12,13,15) 8/29/

71 Example 6 continue.. f (, B, C, D) m(4,5,8,9,11,12,13,15) CD CD CD CD CD Simplified Boolean expression BC f BC C D C D 8/29/

72 Example 7 Minimize the following Boolean expression using K-map ; f 2(, B, C, D) m(0,1,2,3,11,12,14,15) 8/29/

73 Example 7 continue.. f 2(, B, C, D) m(0,1,2,3,11,12,14,15) CD CD CD CD CD Simplified Boolean expression D CD f 2 D CD 8/29/

74 Example 8 Solve the following expression with K-maps; f 1(, B, C) m(0,1,3,4,5) f 2(, B, C) m(0,1,2,3,6,7) 8/29/

75 Example 8 continue f 1(, B, C) m(0,1,3,4,5) f 2(, B, C) m(0,1,2,3,6,7) C BC BC 00 BC 01 BC 11 BC B Simplified Boolean expression f 1 C B BC BC 00 BC 01 BC 11 BC Simplified Boolean expression f 2 B B 8/29/

76 Example 9 Simplify ; f (, B, C, D) m(0,1,4,5,7,8,9,12,13,15) 8/29/

77 Example 9 continue.. CD CD CD CD CD f (, B, C, D) m(0,1,4,5,7,8,9,12,13,15) Simplified Boolean expression f C BD C BD 8/29/

78 Example 10 Solve the following expression with K-maps; f 1(, B, C, D) m(0,1,3,4,5,7) f 2(, B, C) m(0,1,3,4,5,7) 8/29/

79 Example 10 continue f 1(, B, C, D) m(0,1,3,4,5,7) f 2(, B, C ) m (0,1,3,4,5,7) CD CD CD CD CD C Simplified Boolean expression D f C D BC BC 00 BC 01 BC 11 BC Simplified Boolean expression 1 8/29/ B f 2 B C C

80 K-map and don t care conditions For SOP form we enter 1 s corresponding to the combinations of input variables which produce a high output and we enter 0 s in the remaining cells of the K-map. For POS form we enter 0 s corresponding to the combinations of input variables which produce a high output and we enter 1 s in the remaining cells of the K-map. 8/29/

81 K-map and don t care conditions But it is not always true that the cells not containing 1 s (in SOP) will contain 0 s, because some combinations of input variable do not occur. lso for some functions the outputs corresponding to certain combinations of input variables do not matter. 8/29/

82 K-map and don t care conditions In such situations we have a freedom to assume a 0 or 1 as output for each of these combinations. These conditions are known as the Don t Care Conditions and in the K-map it is represented as X, in the corresponding cell. The don t care conditions may be assumed to be 0 or 1 as per the need for simplification 8/29/

83 K-map and don t care conditions - Example Simplify ; f (, B, C, D) m(1,3,7,11,15) d(0,2,5) 8/29/

84 K-map and don t care conditions - Example f (, B, C, D) m(1,3,7,11,15) d(0,2,5) CD CD CD CD CD X X X Simplified Boolean expression f CD D D CD 8/29/2017 mit Nevase 84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

This form sometimes used in logic circuit, example:

This form sometimes used in logic circuit, example: Objectives: 1. Deriving of logical expression form truth tables. 2. Logical expression simplification methods: a. Algebraic manipulation. b. Karnaugh map (k-map). 1. Deriving of logical expression from

More information

Unit 2 Session - 6 Combinational Logic Circuits

Unit 2 Session - 6 Combinational Logic Circuits Objectives Unit 2 Session - 6 Combinational Logic Circuits Draw 3- variable and 4- variable Karnaugh maps and use them to simplify Boolean expressions Understand don t Care Conditions Use the Product-of-Sums

More information

Lecture 6: Manipulation of Algebraic Functions, Boolean Algebra, Karnaugh Maps

Lecture 6: Manipulation of Algebraic Functions, Boolean Algebra, Karnaugh Maps EE210: Switching Systems Lecture 6: Manipulation of Algebraic Functions, Boolean Algebra, Karnaugh Maps Prof. YingLi Tian Feb. 21/26, 2019 Department of Electrical Engineering The City College of New York

More information

Combinational Logic Design/Circuits

Combinational Logic Design/Circuits 3 ` Combinational Logic Design/Circuits Chapter-3(Hours : 12 Marks:24 ) Combinational Logic design / Circuits 3.1 Simplification of Boolean expression using Boolean algebra. 3.2 Construction of logical

More information

Lecture 5: NAND, NOR and XOR Gates, Simplification of Algebraic Expressions

Lecture 5: NAND, NOR and XOR Gates, Simplification of Algebraic Expressions EE210: Switching Systems Lecture 5: NAND, NOR and XOR Gates, Simplification of Algebraic Expressions Prof. YingLi Tian Feb. 15, 2018 Department of Electrical Engineering The City College of New York The

More information

Karnaugh Map & Boolean Expression Simplification

Karnaugh Map & Boolean Expression Simplification Karnaugh Map & Boolean Expression Simplification Mapping a Standard POS Expression For a Standard POS expression, a 0 is placed in the cell corresponding to the product term (maxterm) present in the expression.

More information

Simplification of Boolean Functions. Dept. of CSE, IEM, Kolkata

Simplification of Boolean Functions. Dept. of CSE, IEM, Kolkata Simplification of Boolean Functions Dept. of CSE, IEM, Kolkata 1 Simplification of Boolean Functions: An implementation of a Boolean Function requires the use of logic gates. A smaller number of gates,

More information

Combinational Logic Circuits Part II -Theoretical Foundations

Combinational Logic Circuits Part II -Theoretical Foundations Combinational Logic Circuits Part II -Theoretical Foundations Overview Boolean Algebra Basic Logic Operations Basic Identities Basic Principles, Properties, and Theorems Boolean Function and Representations

More information

211: Computer Architecture Summer 2016

211: Computer Architecture Summer 2016 211: Computer Architecture Summer 2016 Liu Liu Topic: Storage Project3 Digital Logic - Storage: Recap - Review: cache hit rate - Project3 - Digital Logic: - truth table => SOP - simplification: Boolean

More information

CHAPTER III BOOLEAN ALGEBRA

CHAPTER III BOOLEAN ALGEBRA CHAPTER III- CHAPTER III CHAPTER III R.M. Dansereau; v.. CHAPTER III-2 BOOLEAN VALUES INTRODUCTION BOOLEAN VALUES Boolean algebra is a form of algebra that deals with single digit binary values and variables.

More information

Digital Logic Design. Combinational Logic

Digital Logic Design. Combinational Logic Digital Logic Design Combinational Logic Minterms A product term is a term where literals are ANDed. Example: x y, xz, xyz, A minterm is a product term in which all variables appear exactly once, in normal

More information

Karnaugh Maps Objectives

Karnaugh Maps Objectives Karnaugh Maps Objectives For Karnaugh Maps of up to 5 variables Plot a function from algebraic, minterm or maxterm form Obtain minimum Sum of Products and Product of Sums Understand the relationship between

More information

UNIT 5 KARNAUGH MAPS Spring 2011

UNIT 5 KARNAUGH MAPS Spring 2011 UNIT 5 KRNUGH MPS Spring 2 Karnaugh Maps 2 Contents Minimum forms of switching functions Two- and three-variable Four-variable Determination of minimum expressions using essential prime implicants Five-variable

More information

CHAPTER III BOOLEAN ALGEBRA

CHAPTER III BOOLEAN ALGEBRA CHAPTER III- CHAPTER III CHAPTER III R.M. Dansereau; v.. CHAPTER III-2 BOOLEAN VALUES INTRODUCTION BOOLEAN VALUES Boolean algebra is a form of algebra that deals with single digit binary values and variables.

More information

Ex: Boolean expression for majority function F = A'BC + AB'C + ABC ' + ABC.

Ex: Boolean expression for majority function F = A'BC + AB'C + ABC ' + ABC. Boolean Expression Forms: Sum-of-products (SOP) Write an AND term for each input combination that produces a 1 output. Write the input variable if its value is 1; write its complement otherwise. OR the

More information

Lecture 6: Gate Level Minimization Syed M. Mahmud, Ph.D ECE Department Wayne State University

Lecture 6: Gate Level Minimization Syed M. Mahmud, Ph.D ECE Department Wayne State University Lecture 6: Gate Level Minimization Syed M. Mahmud, Ph.D ECE Department Wayne State University Original Source: Aby K George, ECE Department, Wayne State University Contents The Map method Two variable

More information

Boolean Algebra and Logic Simplification

Boolean Algebra and Logic Simplification S302 Digital Logic Design Boolean Algebra and Logic Simplification Boolean Analysis of Logic ircuits, evaluating of Boolean expressions, representing the operation of Logic circuits and Boolean expressions

More information

Ch 2. Combinational Logic. II - Combinational Logic Contemporary Logic Design 1

Ch 2. Combinational Logic. II - Combinational Logic Contemporary Logic Design 1 Ch 2. Combinational Logic II - Combinational Logic Contemporary Logic Design 1 Combinational logic Define The kind of digital system whose output behavior depends only on the current inputs memoryless:

More information

ENGG 1203 Tutorial - 2 Recall Lab 2 - e.g. 4 input XOR. Parity checking (for interest) Recall : Simplification methods. Recall : Time Delay

ENGG 1203 Tutorial - 2 Recall Lab 2 - e.g. 4 input XOR. Parity checking (for interest) Recall : Simplification methods. Recall : Time Delay ENGG 23 Tutorial - 2 Recall Lab 2 - e.g. 4 input XOR Parity checking (for interest) Parity bit Parity checking Error detection, eg. Data can be Corrupted Even parity total number of s is even Odd parity

More information

EECS150 - Digital Design Lecture 19 - Combinational Logic Circuits : A Deep Dive

EECS150 - Digital Design Lecture 19 - Combinational Logic Circuits : A Deep Dive EECS150 - Digital Design Lecture 19 - Combinational Logic Circuits : A Deep Dive March 30, 2010 John Wawrzynek Spring 2010 EECS150 - Lec19-cl1 Page 1 Boolean Algebra I (Representations of Combinational

More information

ENG2410 Digital Design Combinational Logic Circuits

ENG2410 Digital Design Combinational Logic Circuits ENG240 Digital Design Combinational Logic Circuits Fall 207 S. Areibi School of Engineering University of Guelph Binary variables Binary Logic Can be 0 or (T or F, low or high) Variables named with single

More information

Review for Test 1 : Ch1 5

Review for Test 1 : Ch1 5 Review for Test 1 : Ch1 5 October 5, 2006 Typeset by FoilTEX Positional Numbers 527.46 10 = (5 10 2 )+(2 10 1 )+(7 10 0 )+(4 10 1 )+(6 10 2 ) 527.46 8 = (5 8 2 ) + (2 8 1 ) + (7 8 0 ) + (4 8 1 ) + (6 8

More information

Logic Simplification. Boolean Simplification Example. Applying Boolean Identities F = A B C + A B C + A BC + ABC. Karnaugh Maps 2/10/2009 COMP370 1

Logic Simplification. Boolean Simplification Example. Applying Boolean Identities F = A B C + A B C + A BC + ABC. Karnaugh Maps 2/10/2009 COMP370 1 Digital Logic COMP370 Introduction to Computer Architecture Logic Simplification It is frequently possible to simplify a logical expression. This makes it easier to understand and requires fewer gates

More information

1. Name the person who developed Boolean algebra

1. Name the person who developed Boolean algebra MATHEMATIC CENTER D96 MUNIRKA VILLAGE NEW DELHI 67 & VIKAS PURI NEW DELHI CONTACT FOR COACHING MATHEMATICS FOR TH 2TH NDA DIPLOMA SSC CAT SAT CPT CONTACT FOR ADMISSION GUIDANCE B.TECH BBA BCA, MCA MBA

More information

MC9211 Computer Organization

MC9211 Computer Organization MC92 Computer Organization Unit : Digital Fundamentals Lesson2 : Boolean Algebra and Simplification (KSB) (MCA) (29-2/ODD) (29 - / A&B) Coverage Lesson2 Introduces the basic postulates of Boolean Algebra

More information

UNIT 4 MINTERM AND MAXTERM EXPANSIONS

UNIT 4 MINTERM AND MAXTERM EXPANSIONS UNIT 4 MINTERM AND MAXTERM EXPANSIONS Spring 2 Minterm and Maxterm Expansions 2 Contents Conversion of English sentences to Boolean equations Combinational logic design using a truth table Minterm and

More information

Review. EECS Components and Design Techniques for Digital Systems. Lec 06 Minimizing Boolean Logic 9/ Review: Canonical Forms

Review. EECS Components and Design Techniques for Digital Systems. Lec 06 Minimizing Boolean Logic 9/ Review: Canonical Forms Review EECS 150 - Components and Design Techniques for Digital Systems Lec 06 Minimizing Boolean Logic 9/16-04 David Culler Electrical Engineering and Computer Sciences University of California, Berkeley

More information

Signals and Systems Digital Logic System

Signals and Systems Digital Logic System Signals and Systems Digital Logic System Prof. Wonhee Kim Chapter 2 Design Process for Combinational Systems Step 1: Represent each of the inputs and outputs in binary Step 1.5: If necessary, break the

More information

Chapter 2 Combinational Logic Circuits

Chapter 2 Combinational Logic Circuits Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Goal: To obtain the simplest implementation for a given function Optimization is a more formal

More information

Introduction to Karnaugh Maps

Introduction to Karnaugh Maps Introduction to Karnaugh Maps Review So far, you (the students) have been introduced to truth tables, and how to derive a Boolean circuit from them. We will do an example. Consider the truth table for

More information

ELC224C. Karnaugh Maps

ELC224C. Karnaugh Maps KARNAUGH MAPS Function Simplification Algebraic Simplification Half Adder Introduction to K-maps How to use K-maps Converting to Minterms Form Prime Implicants and Essential Prime Implicants Example on

More information

II. COMBINATIONAL LOGIC DESIGN. - algebra defined on a set of 2 elements, {0, 1}, with binary operators multiply (AND), add (OR), and invert (NOT):

II. COMBINATIONAL LOGIC DESIGN. - algebra defined on a set of 2 elements, {0, 1}, with binary operators multiply (AND), add (OR), and invert (NOT): ENGI 386 Digital Logic II. COMBINATIONAL LOGIC DESIGN Combinational Logic output of digital system is only dependent on current inputs (i.e., no memory) (a) Boolean Algebra - developed by George Boole

More information

Chapter 7 Logic Circuits

Chapter 7 Logic Circuits Chapter 7 Logic Circuits Goal. Advantages of digital technology compared to analog technology. 2. Terminology of Digital Circuits. 3. Convert Numbers between Decimal, Binary and Other forms. 5. Binary

More information

ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN ELCT2: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 2 Following the slides of Dr. Ahmed H. Madian ذو الحجة 438 ه Winter

More information

Chapter 2 : Boolean Algebra and Logic Gates

Chapter 2 : Boolean Algebra and Logic Gates Chapter 2 : Boolean Algebra and Logic Gates By Electrical Engineering Department College of Engineering King Saud University 1431-1432 2.1. Basic Definitions 2.2. Basic Theorems and Properties of Boolean

More information

Gate-Level Minimization

Gate-Level Minimization Gate-Level Minimization Dr. Bassem A. Abdullah Computer and Systems Department Lectures Prepared by Dr.Mona Safar, Edited and Lectured by Dr.Bassem A. Abdullah Outline 1. The Map Method 2. Four-variable

More information

The Karnaugh Map COE 202. Digital Logic Design. Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals

The Karnaugh Map COE 202. Digital Logic Design. Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals The Karnaugh Map COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals Presentation Outline Boolean Function Minimization The Karnaugh Map (K-Map) Two, Three,

More information

Combinational Logic Fundamentals

Combinational Logic Fundamentals Topic 3: Combinational Logic Fundamentals In this note we will study combinational logic, which is the part of digital logic that uses Boolean algebra. All the concepts presented in combinational logic

More information

Design of Combinational Logic

Design of Combinational Logic Pune Vidyarthi Griha s COLLEGE OF ENGINEERING, NASHIK 3. Design of Combinational Logic By Prof. Anand N. Gharu (Assistant Professor) PVGCOE Computer Dept.. 30 th June 2017 CONTENTS :- 1. Code Converter

More information

Boolean Algebra and Digital Logic 2009, University of Colombo School of Computing

Boolean Algebra and Digital Logic 2009, University of Colombo School of Computing IT 204 Section 3.0 Boolean Algebra and Digital Logic Boolean Algebra 2 Logic Equations to Truth Tables X = A. B + A. B + AB A B X 0 0 0 0 3 Sum of Products The OR operation performed on the products of

More information

for Digital Systems Simplification of logic functions Tajana Simunic Rosing Sources: TSR, Katz, Boriello & Vahid

for Digital Systems Simplification of logic functions Tajana Simunic Rosing Sources: TSR, Katz, Boriello & Vahid SE140: omponents and Design Techniques for Digital Systems Simplification of logic functions Tajana Simunic Rosing 1 What we covered thus far: Number representations Where we are now inary, Octal, Hex,

More information

CHAPTER 5 KARNAUGH MAPS

CHAPTER 5 KARNAUGH MAPS CHAPTER 5 1/36 KARNAUGH MAPS This chapter in the book includes: Objectives Study Guide 5.1 Minimum Forms of Switching Functions 5.2 Two- and Three-Variable Karnaugh Maps 5.3 Four-Variable Karnaugh Maps

More information

CPE100: Digital Logic Design I

CPE100: Digital Logic Design I Chapter 2 Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu http://www.ee.unlv.edu/~b1morris/cpe100/ CPE100: Digital Logic Design I Section 1004: Dr. Morris Combinational Logic Design Chapter

More information

Standard Expression Forms

Standard Expression Forms ThisLecture will cover the following points: Canonical and Standard Forms MinTerms and MaxTerms Digital Logic Families 24 March 2010 Standard Expression Forms Two standard (canonical) expression forms

More information

Theorem/Law/Axioms Over (.) Over (+)

Theorem/Law/Axioms Over (.) Over (+) material prepared by: MUKESH OHR Follow me on F : http://www.facebook.com/mukesh.sirji4u OOLEN LGER oolean lgebra is a set of rules, laws and theorems by which logical operations can be mathematically

More information

Midterm1 Review. Jan 24 Armita

Midterm1 Review. Jan 24 Armita Midterm1 Review Jan 24 Armita Outline Boolean Algebra Axioms closure, Identity elements, complements, commutativity, distributivity theorems Associativity, Duality, De Morgan, Consensus theorem Shannon

More information

Advanced Digital Design with the Verilog HDL, Second Edition Michael D. Ciletti Prentice Hall, Pearson Education, 2011

Advanced Digital Design with the Verilog HDL, Second Edition Michael D. Ciletti Prentice Hall, Pearson Education, 2011 Problem 2-1 Recall that a minterm is a cube in which every variable appears. A Boolean expression in SOP form is canonical if every cube in the expression has a unique representation in which all of the

More information

DIGITAL ELECTRONICS & it0203 Semester 3

DIGITAL ELECTRONICS & it0203 Semester 3 DIGITAL ELECTRONICS & it0203 Semester 3 P.Rajasekar & C.M.T.Karthigeyan Asst.Professor SRM University, Kattankulathur School of Computing, Department of IT 8/22/2011 1 Disclaimer The contents of the slides

More information

Administrative Notes. Chapter 2 <9>

Administrative Notes. Chapter 2 <9> Administrative Notes Note: New homework instructions starting with HW03 Homework is due at the beginning of class Homework must be organized, legible (messy is not), and stapled to be graded Chapter 2

More information

CHAPTER 7. Solutions for Exercises

CHAPTER 7. Solutions for Exercises CHAPTER 7 Solutions for Exercises E7.1 (a) For the whole part we have: Quotient Remainders 23/2 11 1 11/2 5 1 5/2 2 1 2/2 1 0 1/2 0 1 Reading the remainders in reverse order we obtain: 23 10 = 10111 2

More information

Chapter 2 Boolean Algebra and Logic Gates

Chapter 2 Boolean Algebra and Logic Gates Ch1: Digital Systems and Binary Numbers Ch2: Ch3: Gate-Level Minimization Ch4: Combinational Logic Ch5: Synchronous Sequential Logic Ch6: Registers and Counters Switching Theory & Logic Design Prof. Adnan

More information

Lecture 5. Karnaugh-Map

Lecture 5. Karnaugh-Map Lecture 5 - Lecture 5 Karnaugh-Map Lecture 5-2 Karnaugh-Map Set Logic Venn Diagram K-map Lecture 5-3 K-Map for 2 Variables Lecture 5-4 K-Map for 3 Variables C C C Lecture 5-5 Logic Expression, Truth Table,

More information

Slide Set 3. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary

Slide Set 3. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary Slide Set 3 for ENEL 353 Fall 2016 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary Fall Term, 2016 SN s ENEL 353 Fall 2016 Slide Set 3 slide

More information

Optimizations and Tradeoffs. Combinational Logic Optimization

Optimizations and Tradeoffs. Combinational Logic Optimization Optimizations and Tradeoffs Combinational Logic Optimization Optimization & Tradeoffs Up to this point, we haven t really considered how to optimize our designs. Optimization is the process of transforming

More information

Why digital? Overview. Number Systems. Binary to Decimal conversion

Why digital? Overview. Number Systems. Binary to Decimal conversion Why digital? Overview It has the following advantages over analog. It can be processed and transmitted efficiently and reliably. It can be stored and retrieved with greater accuracy. Noise level does not

More information

Chapter 2 Combinational Logic Circuits

Chapter 2 Combinational Logic Circuits Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 1 Gate Circuits and Boolean Equations Charles Kime & Thomas Kaminski 2008 Pearson Education, Inc. (Hyperlinks are active

More information

LOGIC GATES. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D.

LOGIC GATES. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D. Basic Eperiment and Design of Electronics LOGIC GATES Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Outline Boolean algebra Logic gates Karnaugh maps

More information

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 2 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 2 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Week 2 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering Boolean Algebra Boolean Algebra A Boolean algebra is defined with: A set of

More information

Karnaugh Maps (K-Maps)

Karnaugh Maps (K-Maps) Karnaugh Maps (K-Maps) Boolean expressions can be minimized by combining terms P + P = P K-maps minimize equations graphically Put terms to combine close to one another B C C B B C BC BC BC BC BC BC BC

More information

CS 121 Digital Logic Design. Chapter 2. Teacher Assistant. Hanin Abdulrahman

CS 121 Digital Logic Design. Chapter 2. Teacher Assistant. Hanin Abdulrahman CS 121 Digital Logic Design Chapter 2 Teacher Assistant Hanin Abdulrahman 1 2 Outline 2.2 Basic Definitions 2.3 Axiomatic Definition of Boolean Algebra. 2.4 Basic Theorems and Properties 2.5 Boolean Functions

More information

CHAPTER1: Digital Logic Circuits Combination Circuits

CHAPTER1: Digital Logic Circuits Combination Circuits CS224: Computer Organization S.KHABET CHAPTER1: Digital Logic Circuits Combination Circuits 1 PRIMITIVE LOGIC GATES Each of our basic operations can be implemented in hardware using a primitive logic gate.

More information

Unit 3 Session - 9 Data-Processing Circuits

Unit 3 Session - 9 Data-Processing Circuits Objectives Unit 3 Session - 9 Data-Processing Design of multiplexer circuits Discuss multiplexer applications Realization of higher order multiplexers using lower orders (multiplexer trees) Introduction

More information

Logic Design Combinational Circuits. Digital Computer Design

Logic Design Combinational Circuits. Digital Computer Design Logic Design Combinational Circuits Digital Computer Design Topics Combinational Logic Karnaugh Maps Combinational uilding locks Timing 2 Logic Circuit logic circuit is composed of: Inputs Outputs Functional

More information

COMBINATIONAL LOGIC FUNCTIONS

COMBINATIONAL LOGIC FUNCTIONS COMBINATIONAL LOGIC FUNCTIONS Digital logic circuits can be classified as either combinational or sequential circuits. A combinational circuit is one where the output at any time depends only on the present

More information

Digital Circuit And Logic Design I. Lecture 4

Digital Circuit And Logic Design I. Lecture 4 Digital Circuit And Logic Design I Lecture 4 Outline Combinational Logic Design Principles (2) 1. Combinational-circuit minimization 2. Karnaugh maps 3. Quine-McCluskey procedure Panupong Sornkhom, 2005/2

More information

EEE130 Digital Electronics I Lecture #4

EEE130 Digital Electronics I Lecture #4 EEE130 Digital Electronics I Lecture #4 - Boolean Algebra and Logic Simplification - By Dr. Shahrel A. Suandi Topics to be discussed 4-1 Boolean Operations and Expressions 4-2 Laws and Rules of Boolean

More information

Karnaugh Maps for Combinatorial Logic CS 64: Computer Organization and Design Logic Lecture #12

Karnaugh Maps for Combinatorial Logic CS 64: Computer Organization and Design Logic Lecture #12 Karnaugh Maps for Combinatorial Logic CS 64: Computer Organization and Design Logic Lecture #2 Ziad Matni Dept. of Computer Science, UCSB Administrative Re: Midterm Exam #2 On Thursday! Everything from

More information

Possible logic functions of two variables

Possible logic functions of two variables ombinational logic asic logic oolean algebra, proofs by re-writing, proofs by perfect induction logic functions, truth tables, and switches NOT, ND, OR, NND, NOR, OR,..., minimal set Logic realization

More information

Z = F(X) Combinational circuit. A combinational circuit can be specified either by a truth table. Truth Table

Z = F(X) Combinational circuit. A combinational circuit can be specified either by a truth table. Truth Table Lesson Objectives In this lesson, you will learn about What are combinational circuits Design procedure of combinational circuits Examples of combinational circuit design Combinational Circuits Logic circuit

More information

If f = ABC + ABC + A B C then f = AB C + A BC + AB C + A BC + A B C

If f = ABC + ABC + A B C then f = AB C + A BC + AB C + A BC + A B C Examples: If f 5 = AB + AB then f 5 = A B + A B = f 10 If f = ABC + ABC + A B C then f = AB C + A BC + AB C + A BC + A B C In terms of a truth table, if f is the sum (OR) of all the minterms with a 1 in

More information

Digital Logic Design. Malik Najmus Siraj

Digital Logic Design. Malik Najmus Siraj Digital Logic Design Malik Najmus Siraj siraj@case.edu.pkedu LECTURE 4 Today s Agenda Recap 2 s complement Binary Logic Boolean algebra Recap Computer Arithmetic Signed numbers Radix and diminished radix

More information

EE40 Lec 15. Logic Synthesis and Sequential Logic Circuits

EE40 Lec 15. Logic Synthesis and Sequential Logic Circuits EE40 Lec 15 Logic Synthesis and Sequential Logic Circuits Prof. Nathan Cheung 10/20/2009 Reading: Hambley Chapters 7.4-7.6 Karnaugh Maps: Read following before reading textbook http://www.facstaff.bucknell.edu/mastascu/elessonshtml/logic/logic3.html

More information

EXPERIMENT #4: SIMPLIFICATION OF BOOLEAN FUNCTIONS

EXPERIMENT #4: SIMPLIFICATION OF BOOLEAN FUNCTIONS EXPERIMENT #4: SIMPLIFICATION OF BOOLEAN FUNCTIONS OBJECTIVES: Simplify Boolean functions using K-map method Obtain Boolean expressions from timing diagrams Design and implement logic circuits Equipment

More information

Logic Design. Chapter 2: Introduction to Logic Circuits

Logic Design. Chapter 2: Introduction to Logic Circuits Logic Design Chapter 2: Introduction to Logic Circuits Introduction Logic circuits perform operation on digital signal Digital signal: signal values are restricted to a few discrete values Binary logic

More information

CMSC 313 Lecture 19 Combinational Logic Components Programmable Logic Arrays Karnaugh Maps

CMSC 313 Lecture 19 Combinational Logic Components Programmable Logic Arrays Karnaugh Maps CMSC 33 Lecture 9 Combinational Logic Components Programmable Logic rrays Karnaugh Maps UMC, CMSC33, Richard Chang Last Time & efore Returned midterm exam Half adders & full adders Ripple

More information

Number System conversions

Number System conversions Number System conversions Number Systems The system used to count discrete units is called number system. There are four systems of arithmetic which are often used in digital electronics. Decimal Number

More information

Chap 2. Combinational Logic Circuits

Chap 2. Combinational Logic Circuits Overview 2 Chap 2. Combinational Logic Circuits Spring 24 Part Gate Circuits and Boolean Equations Binary Logic and Gates Boolean Algebra Standard Forms Part 2 Circuit Optimization Two-Level Optimization

More information

14:332:231 DIGITAL LOGIC DESIGN. Combinational Circuit Synthesis

14:332:231 DIGITAL LOGIC DESIGN. Combinational Circuit Synthesis :: DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University Electrical & Computer Engineering all Lecture #: Combinational Circuit Synthesis I Combinational Circuit Synthesis Recall: Combinational circuit

More information

Systems I: Computer Organization and Architecture

Systems I: Computer Organization and Architecture Systems I: Computer Organization and Architecture Lecture 6 - Combinational Logic Introduction A combinational circuit consists of input variables, logic gates, and output variables. The logic gates accept

More information

Chapter 2 Combinational logic

Chapter 2 Combinational logic Chapter 2 Combinational logic Chapter 2 is very easy. I presume you already took discrete mathemtics. The major part of chapter 2 is boolean algebra. II - Combinational Logic Copyright 24, Gaetano Borriello

More information

Combinational Logic. By : Ali Mustafa

Combinational Logic. By : Ali Mustafa Combinational Logic By : Ali Mustafa Contents Adder Subtractor Multiplier Comparator Decoder Encoder Multiplexer How to Analyze any combinational circuit like this? Analysis Procedure To obtain the output

More information

Chapter 5. Karnaugh Map and Minimization Procedures

Chapter 5. Karnaugh Map and Minimization Procedures hapter 5 Karnaugh Map and Minimization Procedures Lesson 1 KARNAUGH MAP h05l1-"digital Principles and Design", Raj Kamal, Pearson Education, 2006 2 Outline Three variable Karnaugh map Four variable Karnaugh

More information

Chapter 2 Combinational Logic Circuits

Chapter 2 Combinational Logic Circuits Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Charles Kime & Thomas Kaminski 2004 Pearson Education, Inc. Terms of Use (Hyperlinks are active

More information

Simplifying Logic Circuits with Karnaugh Maps

Simplifying Logic Circuits with Karnaugh Maps Simplifying Logic Circuits with Karnaugh Maps The circuit at the top right is the logic equivalent of the Boolean expression: f = abc + abc + abc Now, as we have seen, this expression can be simplified

More information

Prove that if not fat and not triangle necessarily means not green then green must be fat or triangle (or both).

Prove that if not fat and not triangle necessarily means not green then green must be fat or triangle (or both). hapter : oolean lgebra.) Definition of oolean lgebra The oolean algebra is named after George ool who developed this algebra (854) in order to analyze logical problems. n example to such problem is: Prove

More information

Total Time = 90 Minutes, Total Marks = 50. Total /50 /10 /18

Total Time = 90 Minutes, Total Marks = 50. Total /50 /10 /18 University of Waterloo Department of Electrical & Computer Engineering E&CE 223 Digital Circuits and Systems Midterm Examination Instructor: M. Sachdev October 23rd, 2007 Total Time = 90 Minutes, Total

More information

Computer Organization I. Lecture 13: Design of Combinational Logic Circuits

Computer Organization I. Lecture 13: Design of Combinational Logic Circuits Computer Organization I Lecture 13: Design of Combinational Logic Circuits Overview The optimization of multiple-level circuits Mapping Technology Verification Objectives To know how to optimize the multiple-level

More information

Boolean Algebra and Logic Design (Class 2.2 1/24/2013) CSE 2441 Introduction to Digital Logic Spring 2013 Instructor Bill Carroll, Professor of CSE

Boolean Algebra and Logic Design (Class 2.2 1/24/2013) CSE 2441 Introduction to Digital Logic Spring 2013 Instructor Bill Carroll, Professor of CSE Boolean Algebra and Logic Design (Class 2.2 1/24/2013) CSE 2441 Introduction to Digital Logic Spring 2013 Instructor Bill Carroll, Professor of CSE Today s Topics Boolean algebra applications in logic

More information

Outcomes. Spiral 1 / Unit 5. Logic Function Synthesis KARNAUGH MAPS. Karnaugh Maps

Outcomes. Spiral 1 / Unit 5. Logic Function Synthesis KARNAUGH MAPS. Karnaugh Maps -. -. Spiral / Unit Mark Redekopp Outcomes I know the difference between combinational and sequential logic and can name examples of each. I understand latency, throughput, and at least technique to improve

More information

Spiral 1 / Unit 5. Karnaugh Maps

Spiral 1 / Unit 5. Karnaugh Maps -. Spiral / Unit Karnaugh Maps -. Outcomes I know the difference between combinational and sequential logic and can name examples of each. I understand latency, throughput, and at least technique to improve

More information

( c) Give logic symbol, Truth table and circuit diagram for a clocked SR flip-flop. A combinational circuit is defined by the function

( c) Give logic symbol, Truth table and circuit diagram for a clocked SR flip-flop. A combinational circuit is defined by the function Question Paper Digital Electronics (EE-204-F) MDU Examination May 2015 1. (a) represent (32)10 in (i) BCD 8421 code (ii) Excess-3 code (iii) ASCII code (b) Design half adder using only NAND gates. ( c)

More information

Logic. Combinational. inputs. outputs. the result. system can

Logic. Combinational. inputs. outputs. the result. system can Digital Electronics Combinational Logic Functions Digital logic circuits can be classified as either combinational or sequential circuits. A combinational circuit is one where the output at any time depends

More information

Chapter 2: Boolean Algebra and Logic Gates

Chapter 2: Boolean Algebra and Logic Gates Chapter 2: Boolean Algebra and Logic Gates Mathematical methods that simplify binary logics or circuits rely primarily on Boolean algebra. Boolean algebra: a set of elements, a set of operators, and a

More information

Chapter-2 BOOLEAN ALGEBRA

Chapter-2 BOOLEAN ALGEBRA Chapter-2 BOOLEAN ALGEBRA Introduction: An algebra that deals with binary number system is called Boolean Algebra. It is very power in designing logic circuits used by the processor of computer system.

More information

L2: Combinational Logic Design (Construction and Boolean Algebra)

L2: Combinational Logic Design (Construction and Boolean Algebra) L2: Combinational Logic Design (Construction and Boolean Algebra) Acknowledgements: Lecture material adapted from Chapter 2 of R. Katz, G. Borriello, Contemporary Logic Design (second edition), Pearson

More information

UNIT II COMBINATIONAL CIRCUITS:

UNIT II COMBINATIONAL CIRCUITS: UNIT II COMBINATIONAL CIRCUITS: INTRODUCTION: The digital system consists of two types of circuits, namely (i) (ii) Combinational circuits Sequential circuits Combinational circuit consists of logic gates

More information

Outcomes. Spiral 1 / Unit 5. Logic Function Synthesis KARNAUGH MAPS. Karnaugh Maps

Outcomes. Spiral 1 / Unit 5. Logic Function Synthesis KARNAUGH MAPS. Karnaugh Maps -. -. Spiral / Unit Mark Redekopp Outcomes I know the difference between combinational and sequential logic and can name examples of each. I understand latency, throughput, and at least technique to improve

More information

BOOLEAN ALGEBRA CLASS XII. Presented By : Dinesh Patel PGT CS KV IIT Powai

BOOLEAN ALGEBRA CLASS XII. Presented By : Dinesh Patel PGT CS KV IIT Powai BOOLEAN ALGEBRA CLASS II Presented By : Dinesh Patel PGT CS KV IIT Powai Introduction Boolean Algebra is a set of rules and regulation which is suitable for Digital Circuits, whose answer is either True

More information

Lecture 2 Review on Digital Logic (Part 1)

Lecture 2 Review on Digital Logic (Part 1) Lecture 2 Review on Digital Logic (Part 1) Xuan Silvia Zhang Washington University in St. Louis http://classes.engineering.wustl.edu/ese461/ Grading Engagement 5% Review Quiz 10% Homework 10% Labs 40%

More information

Karnaugh Maps ف ر آ ا د : ا ا ب ا م آ ه ا ن ر ا

Karnaugh Maps ف ر آ ا د : ا ا ب ا م آ ه ا ن ر ا Karnaugh Maps مخطط آارنوف اعداد:محمد اسماعيل آلية علوم الحاسوب جامعة امدرمان الاهلية الاهداء الي آل من يسلك طريق العلم والمعرفة في هذا المجال Venn Diagrams Venn diagram to represent the space of minterms.

More information