CMSC 313 Preview Slides

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1 CMSC 33 Preview Slies These are raft slies. The actual slies presente in lecture may be ifferent ue to last minute changes, scheule slippage,... UMBC, CMSC33, Richar Chang

2 CMSC 33 Lecture 2 Introuction to Circuit Simplification Karnaugh Map eamples Quine-McCluskey (Tabular Reuction) UMBC, CMSC33, Richar Chang <chang@umbc.eu>

3 B-3 Appeni B: Reuction of Digital Logic Reuction (Simplification) of Boolean Epressions It is usually possible to simplify the canonical SOP (or POS) forms. A smaller Boolean equation generally translates to a lower gate count in the target circuit. We cover three methos: algebraic reuction, Karnaugh map reuction, an tabular (Quine-McCluskey) reuction. Principles of Computer Architecture by M. Murocca an V. Heuring 999 M. Murocca an V. Heuring

4 B-7 Appeni B: Reuction of Digital Logic Karnaugh Maps: Venn Diagram Representation of Majority Function Each istinct region in the Universe represents a minterm. This iagram can be transforme into a Karnaugh Map. ABC A ABC AB C AB C A BC A B C A BC A B C B C Principles of Computer Architecture by M. Murocca an V. Heuring 999 M. Murocca an V. Heuring

5 B-8 Appeni B: Reuction of Digital Logic K-Map for Majority Function Place a in each cell that correspons to that minterm. Cells on the outer ege of the map wrap aroun Minterm Ine A B C F C AB -sie -sie A balance tips to the left or right epening on whether there are more s or s. Principles of Computer Architecture by M. Murocca an V. Heuring 999 M. Murocca an V. Heuring

6 B-9 Appeni B: Reuction of Digital Logic Ajacency Groupings for Majority Function C AB F = BC + AC + AB Principles of Computer Architecture by M. Murocca an V. Heuring 999 M. Murocca an V. Heuring

7 B- Appeni B: Reuction of Digital Logic Minimize AND-OR Majority Circuit A B C F F = BC + AC + AB The K-map approach yiels the same minimal two-level form as the algebraic approach. Principles of Computer Architecture by M. Murocca an V. Heuring 999 M. Murocca an V. Heuring

8 B- Appeni B: Reuction of Digital Logic K-Map Groupings Minimal grouping is on the left, non-minimal (but logically equivalent) grouping is on the right. To obtain minimal grouping, create smallest groups first. AB CD AB CD F = A B C + A C D + A B C + A C D F = B D + A B C + A C D + A B C + A C D Principles of Computer Architecture by M. Murocca an V. Heuring 999 M. Murocca an V. Heuring

9 Eample Requiring More Rules A AB CD D C B UMBC, CMSC33, Richar Chang <chang@umbc.eu>

10 B-2 Appeni B: Reuction of Digital Logic K-Map Corners are Logically Ajacent CD AB F = B C D + B D + A B Principles of Computer Architecture by M. Murocca an V. Heuring 999 M. Murocca an V. Heuring

11 B-3 Appeni B: Reuction of Digital Logic K-Maps an Don t Cares There can be more than one minimal grouping, as a result of on t cares. AB CD AB CD F = B C D + B D F = A B D + B D Principles of Computer Architecture by M. Murocca an V. Heuring 999 M. Murocca an V. Heuring

12 Two bits:,,, Gray Coe Three bits:,,,,,,, Successive bit patterns only iffer at position For Karnaugh maps, ajacent s represent minterms that can be simplifie using the rule: ABC + A BC = (A + A )BC = BC = BC A AB C UMBC, CMSC33, Richar Chang <chang@umbc.eu> B

13 Karnaugh Maps Implicant: rectangle with, 2, 4, 8, 6... s Prime Implicant: an implicant that cannot be etene into a larger implicant Essential Prime Implicant: the only prime implicant that covers some K-map Algorithm (not from M&H):. Fin ALL the prime implicants. Be sure to check every an to use on t cares. 2. Inclue all essential prime implicants. 3. Try all possibilities to fin the minimum cover for the remaining s. UMBC, CMSC33, Richar Chang <chang@umbc.eu>

14 K-map Eample A AB CD A AB CD D D C C B B A B + AC D + AB D UMBC, CMSC33, Richar Chang <chang@umbc.eu>

15 Notes on K-maps Also works for POS Takes 2 n time for formulas with n variables Only optimizes two-level logic Reuces number of terms, then number of literals in each term Assumes inverters are free Does not consier minimizations across functions Circuit minimization is generally a har problem Quine-McCluskey can be use with more variables CAD tools are available if you are serious UMBC, CMSC33, Richar Chang <chang@umbc.eu>

16 Karnaugh Maps Implicant: rectangle with, 2, 4, 8, 6... s Prime Implicant: an implicant that cannot be etene into a larger implicant Essential Prime Implicant: the only prime implicant that covers some K-map Algorithm (not from M&H):. Fin ALL the prime implicants. Be sure to check every an to use on t cares. 2. Inclue all essential prime implicants. 3. Try all possibilities to fin the minimum cover for the remaining s. UMBC, CMSC33, Richar Chang <chang@umbc.eu>

17 Notes on K-maps Also works for POS Takes 2 n time for formulas with n variables Only optimizes two-level logic Reuces number of terms, then number of literals in each term Assumes inverters are free Does not consier minimizations across functions Circuit minimization is generally a har problem Quine-McCluskey can be use with more variables CAD tools are available if you are serious UMBC, CMSC33, Richar Chang <chang@umbc.eu>

18 Circuit Minimization is Har Uni systems store passwors in encrypte form. User types in, system computes f() an looks for f() in a file. Suppose we us 64-bit passwors an I want to fin the passwor, such that f() = y. Let gi() = if f() = y an the ith bit of is otherwise. If the ith bit of is, then gi() outputs for every an has a very, very simple circuit. If you can simplify every circuit quickly, then you can crack passwors quickly. UMBC, CMSC33, Richar Chang <chang@umbc.eu>

19 B-6 Appeni B: Reuction of Digital Logic 3-Level Majority Circuit K-Map Reuction results in a reuce two-level circuit (that is, AND followe by OR. Inverters are not inclue in the two-level count). Algebraic reuction can result in multi-level circuits with even fewer logic gates an fewer inputs to the logic gates. A B C M Principles of Computer Architecture by M. Murocca an V. Heuring 999 M. Murocca an V. Heuring

20 CD AB A CD AB A CD AB A D D D C C C B B B CD AB A CD AB A CD AB A D D D C C C B B B

21 B-4 Appeni B: Reuction of Digital Logic Five-Variable K-Map Visualize two 4-variable K-maps stacke one on top of the other; groupings are mae in three imensional cubes. CDE AB AB CDE F = A C D E + A B D E + B E Principles of Computer Architecture by M. Murocca an V. Heuring 999 M. Murocca an V. Heuring

22 B-5 Si-Variable K-Map Appeni B: Reuction of Digital Logic Visualize four 4-variable K-maps stacke one on top of the other; groupings are mae in three imensional cubes. ABC DEF ABC DEF ABC ABC DEF DEF Principles of Computer Architecture by M. Murocca an V. Heuring G = B C E F + A B D E 999 M. Murocca an V. Heuring

23 Appeni B: Reuction of Digital Logic B-9 Principles of Computer Architecture by M. Murocca an V. Heuring 999 M. Murocca an V. Heuring Truth Table with Don t Cares A truth table representation of a single function with on t cares. C D B F A

24 Appeni B: Reuction of Digital Logic B-2 Principles of Computer Architecture by M. Murocca an V. Heuring 999 M. Murocca an V. Heuring Tabular (Quine-McCluskey) Reuction Tabular reuction begins by grouping minterms for which F is nonzero accoring to the number of s in each minterm. Don t cares are consiere to be nonzero. The net step forms a consensus (the logical form of a cross prouct) between each pair of ajacent groups for all terms that iffer in only one variable. C D B A C D B A * * * C D B A * * * Initial setup After first reuction After secon reuction (a) (b) (c)

25 B-2 Appeni B: Reuction of Digital Logic Table of Choice The prime implicants form a set that completely covers the function, although not necessarily minimally. A table of choice is use to obtain a minimal cover set. Prime Implicants Minterms * * * Principles of Computer Architecture by M. Murocca an V. Heuring 999 M. Murocca an V. Heuring

26 B-22 Appeni B: Reuction of Digital Logic Reuce Table of Choice In a reuce table of choice, the essential prime implicants an the minterms they cover are remove, proucing the eligible set. F = ABC + ABC + BD + AD Eligible Set Minterms Set Set 2 X Y Z Principles of Computer Architecture by M. Murocca an V. Heuring 999 M. Murocca an V. Heuring

27 B-23 Appeni B: Reuction of Digital Logic Multiple Output Truth Table The power of tabular reuction comes into play for multiple functions, in which minterms can be share among the functions. Minterm A B C F F F 2 m m m 2 m 3 m 4 m 5 m 6 m 7 Principles of Computer Architecture by M. Murocca an V. Heuring 999 M. Murocca an V. Heuring

28 B-24 Appeni B: Reuction of Digital Logic Multiple Output Table of Choice F (A,B,C) = ABC + BC F (A,B,C) = AC + AC + BC F 2 (A,B,C) = B Minterms Prime Implicants F F * * F (A,B,C) F (A,B,C) F 2 (A,B,C) m m 3 m 7 m m 3 m 4 m 6 m 7 m 2 m 3 m 6 m 7 F * F 2 * F,2 F,,2 * Principles of Computer Architecture by M. Murocca an V. Heuring 999 M. Murocca an V. Heuring

29 Simplifying Finite State Machines State Reuction: equivalent FSM with fewer states State Assignment: choose an assignment of bit patterns to states (e.g., B is ) that results in a smaller circuit Choice of flip-flops: use D flip-flops, J-K flip-flops or a T flip-flops? a goo choice coul lea to simpler circuits. UMBC, CMSC33, Richar Chang <chang@umbc.eu>

30 B-32 Appeni B: Reuction of Digital Logic The State Assignment Problem Two state assignments for machine M 2. Input X P.S. A B/ A/ B C/ D/ C C/ D/ D B/ A/ Input X S S A: / / B: / / C: / / D: / / Input X S S A: / / B: / / C: / / D: / / Machine M 2 State assignment SA State assignment SA Principles of Computer Architecture by M. Murocca an V. Heuring 999 M. Murocca an V. Heuring

31 B-33 Appeni B: Reuction of Digital Logic State Assignment SA Boolean equations for machine M 2 using state assignment SA. S S X X S S X S S S = S S + S S S = S S X + S S X + S S X + S S X Z = S S + S X + S S X Principles of Computer Architecture by M. Murocca an V. Heuring 999 M. Murocca an V. Heuring

32 B-34 Appeni B: Reuction of Digital Logic State Assignment SA Boolean equations for machine M 2 using state assignment SA. S S X X S S X S S S = S S = X Z = S X + S X Principles of Computer Architecture by M. Murocca an V. Heuring 999 M. Murocca an V. Heuring

33 State Assignment Heuristics No known efficient alg. for best state assignment Some heuristics (rules of thumb): The initial state shoul be simple to reset all zeroes or all ones. Minimize the number of state variables that change on each transition. Maimize the number of state variables that on't change on each transition. Eploit symmetries in the state iagram. If there are unuse states (when the number of states s is not a power of 2), choose the unuse state variable combinations carefully. (Don't just use the first s combination of state variables.) Decompose the set of state variables into bits or fiels that have well-efine meaning with respect to the input or output behavior. Consier using more than the minimum number of states to achieve the objectives above. UMBC, CMSC33, Richar Chang <chang@umbc.eu>

34 B-35 Appeni B: Reuction of Digital Logic Sequence Detector State Transition Diagram / / D B / / / E / A / / / F / / C / Input: Output: / G Time: / Principles of Computer Architecture by M. Murocca an V. Heuring 999 M. Murocca an V. Heuring

35 B-36 Appeni B: Reuction of Digital Logic Sequence Detector State Table Present state Input X A B/ C/ B D/ E/ C F/ G/ D D/ E/ E F/ G/ F D/ E/ G F/ G/ Principles of Computer Architecture by M. Murocca an V. Heuring 999 M. Murocca an V. Heuring

36 Sequence Detector State Reuction Table A B C D E F G A B C D E F G UMBC, CMSC33, Richar Chang <chang@umbc.eu>

37 B-37 Appeni B: Reuction of Digital Logic Sequence Detector Reuce State Table Present state Input X A: A' BD: B' C: C' E: D' F: E' G: F' B'/ B'/ E'/ E'/ B'/ E'/ C'/ D'/ F'/ F'/ D'/ F'/ Principles of Computer Architecture by M. Murocca an V. Heuring 999 M. Murocca an V. Heuring

38 6-State Sequence Detector / B/D / E / / / / A F / / / / C / G UMBC, CMSC 33, Richar Chang <chang@umbc.eu>

39 B-38 Appeni B: Reuction of Digital Logic Sequence Detector State Assignment Present state Input X S 2 S S S 2 S S Z S 2 S S Z A': / / B': / / C': / / D': / / E': / / F': / / Principles of Computer Architecture by M. Murocca an V. Heuring 999 M. Murocca an V. Heuring

40 B-4 Appeni B: Reuction of Digital Logic Sequence Detector K-Maps K-map reuction of net state an output functions for sequence etector. S 2 S S X S = S 2 S X + S X + S 2 S + S X S 2 S S X S = S 2 S X + S 2 S X S 2 S S X S 2 S S X S 2 = S 2 S + S Principles of Computer Architecture by M. Murocca an V. Heuring Z = S 2 S X + S S X + S 2 S X 999 M. Murocca an V. Heuring

41 Improve Sequence Detector? Formulas from the 7-state FSM: s2 = (s + )(s2 + s + s) s = s + s = s or s = z = s2 s + s2 s Formulas from the 6-state FSM: s2 = s2 s + s s = s2 s + s2 s s = s2 s + s + s2 s + s z = s2 s + s s + s2 s UMBC, CMSC33, Richar Chang <chang@umbc.eu>

42 Sequence Detector State Assignment 7-state s2 s s s2' s' s' z A = E = B = F = C = G = D = new 6-state s2 s s s2' s' s' z A = E = B/D = F = C = G = D = UMBC, CMSC33, Richar Chang <chang@umbc.eu>

43 6-State Sequence Detector 7-state s2 s s2 s new 6-state s2 s s2 s s s s s s2 = (s + )(s2 + s + s) s2 = (s + )(s2 + s + s) UMBC, CMSC33, Richar Chang <chang@umbc.eu>

44 6-State Sequence Detector 7-state s2 s s2 s new 6-state s2 s s2 s s s s s s = s + s s = s UMBC, CMSC33, Richar Chang <chang@umbc.eu>

45 6-State Sequence Detector 7-state s2 s s2 s new 6-state s2 s s2 s s s s s s = s = UMBC, CMSC33, Richar Chang <chang@umbc.eu>

46 6-State Sequence Detector 7-state s2 s s2 s new 6-state s2 s s2 s s s s s z = s2 s + s2 s z = s2 s + s2 s UMBC, CMSC33, Richar Chang <chang@umbc.eu>

47 Improve Sequence Detector Tetbook formulas for the 6-state FSM: s2 = s2 s + s s = s2 s + s2 s s = s2 s + s + s2 s + s z = s2 s + s s + s2 s New formulas for the 6-state FSM: s2 = (s + )(s2 + s + s) s = s s = z = s2 s + s2 s UMBC, CMSC33, Richar Chang <chang@umbc.eu>

48 B-43 Appeni B: Reuction of Digital Logic Ecitation Tables Each table shows the settings that must be applie at the inputs at time t in orer to change the outputs at time t+. S-R flip-flop Q t Q t+ Q t Q t+ S J R K D flip-flop Q t Q t+ Q t Q t+ D T J-K flip-flop T flip-flop Principles of Computer Architecture by M. Murocca an V. Heuring 999 M. Murocca an V. Heuring

49 B-44 Appeni B: Reuction of Digital Logic Serial Aer Time (t) Time (t) X Y C in Serial Aer Z C out i y i No carry state / / A / Carry state B / / z i / / / State transition iagram, state table, an state assignment for a serial aer. Input XY Present state A A/ A/ A/ B/ B A/ B/ B/ B/ Net state Output Present state (S t ) Input XY A: / / / / B: / / / / Principles of Computer Architecture by M. Murocca an V. Heuring 999 M. Murocca an V. Heuring

50 Appeni B: Reuction of Digital Logic B-45 Principles of Computer Architecture by M. Murocca an V. Heuring 999 M. Murocca an V. Heuring Serial Aer Net-State Functions Truth table showing net-state functions for a serial aer for D, S-R, T, an J-K flip-flops. Shae functions are use in the eample. Y S t X D S R J K T Z Present State (Set) (Reset)

51 B-46 Appeni B: Reuction of Digital Logic J-K Flip-Flop Serial Aer Circuit X Y X Y CLK J Q S K Q X Y Y Z X Principles of Computer Architecture by M. Murocca an V. Heuring 999 M. Murocca an V. Heuring

52 B-47 Appeni B: Reuction of Digital Logic D Flip-Flop Serial Aer Circuit X Y X Y CLK D Q S Q X Y Y Z X Principles of Computer Architecture by M. Murocca an V. Heuring 999 M. Murocca an V. Heuring

53 B-35 Appeni B: Reuction of Digital Logic Sequence Detector State Transition Diagram / / D B / / / E / A / / / F / / C / Input: Output: / G Time: / Principles of Computer Architecture by M. Murocca an V. Heuring 999 M. Murocca an V. Heuring

54 6-State Sequence Detector / B/D / E / / / / A F / / / / C / G UMBC, CMSC 33, Richar Chang <chang@umbc.eu>

55 Improve Sequence Detector? Formulas from the 7-state FSM: s2 = (s + )(s2 + s + s) s = s + s = s or s = z = s2 s + s2 s Formulas from the 6-state FSM: s2 = s2 s + s s = s2 s + s2 s s = s2 s + s + s2 s + s z = s2 s + s s + s2 s UMBC, CMSC33, Richar Chang <chang@umbc.eu>

56 Sequence Detector State Assignment 7-state s2 s s s2' s' s' z A = E = B = F = C = G = D = new 6-state s2 s s s2' s' s' z A = E = B/D = F = C = G = D = UMBC, CMSC33, Richar Chang <chang@umbc.eu>

57 Improve Sequence Detector Tetbook formulas for the 6-state FSM: s2 = s2 s + s s = s2 s + s2 s s = s2 s + s + s2 s + s z = s2 s + s s + s2 s New formulas for the 6-state FSM: s2 = (s + )(s2 + s + s) s = s s = z = s2 s + s2 s UMBC, CMSC33, Richar Chang <chang@umbc.eu>

58 6-State Sequence Detector s2 s s s2' s' s' z j2 k2 j k j k Q Q' J K UMBC, CMSC33, Richar Chang <chang@umbc.eu>

59 6-State Sequence Detector J2 s2 s s2 s K2 s2 s s2 s s s s s J2 = s + s K2 = s UMBC, CMSC33, Richar Chang <chang@umbc.eu>

60 6-State Sequence Detector J s2 s s2 s K s2 s s2 s s s s s J = s K = UMBC, CMSC33, Richar Chang <chang@umbc.eu>

61 6-State Sequence Detector J s2 s s2 s K s2 s s2 s s s s s J = K = UMBC, CMSC33, Richar Chang <chang@umbc.eu>

62 Improve Sequence Detector Formulas for the 6-state FSM with D Flip-flops: s2 = (s + )(s2 + s + s) s = s s = Formulas for the 6-state FSM with J-K Flip-flops: J2 = s + s J = s J = K2 = s K = K = UMBC, CMSC33, Richar Chang <chang@umbc.eu>

63 CMSC 33 Computer Organization & Assembly Language Programming Section Fall 24 Homework 5 Due: Tuesay, December 7, 23. ( points) Question A.3, page 494, Murocca & Heuring 2. ( points) Question A.29, page 497, Murocca & Heuring 3. ( points) Question B., page 542, Murocca & Heuring 4. ( points) Question B., page 542, Murocca & Heuring 5. (6 points) This problem asks you to take the steps involve in the esign process of a finite state machine. You will esign a finite state machine that has a one bit input an a one bit output z. Themachinemustoutputforeveryinputsequenceening in the string or. The output shoul be in all other cases. [Aapte from Contemporary Logic Design, Rany H.Katz,Benjamin/Cummings Publishing, 994.] (a) ( points) In the space provie on the net page, raw the minimumstatetransition iagram for the finite state machine escribe above. You must use the state-minimization algorithm escribe in class to show that the finite state machine has the minimum number of states. (Hint: You shoul have fewer than 8statesinyourmachine.) (b) (5 points) Use the state assignment heuristics escribe in class an pick two ifferent state assignments for your finite state machine. Note: the bit pattern for the initial state must be. (c) (4 points) For each of the two state assignments: i. Fill in the truth tables with values for D flip-flops, for the output bit an for J-K flip-flops. ii. Use the Karnaugh maps provie to minimize the formulas for each column of the truth table. iii. Count the number of gates neee for each implementation. () (5 points) Shoul you use your first or secon state assignment? D flip-flops or J-K flip-flops? Note: Keep a copy of your work for the last question. You will nee it for DigSim Assignment 3.

64 CMSC 33 Homework 5 Name: Minimize State Transition Diagram (show work) State Assignment: A B C D E F unuse unuse Assignment # Assignment#2

65 ASSIGNMENT # Ecitation Table for J-K Flip-Flops Q Q' J K Truth Table: s2 s s s2' s' s' z j2 k2 j k j k

66 Assignment #: Karnaugh Maps for D Flip-Flops an the output s2 s2 s s s2 s2 s s s s s s s2 = s = # of gates = # of gates = s2 s2 s s s2 s2 s s s s s s s = z = # of gates = # of gates = Total # of gates for D flip-flops (on t count z) =

67 Assignment #: Karnaugh Maps for J-K Flip-Flops s2 s2 s s s2 s2 s s s s s j2 = k2 = # of gates = # of gates = s s2 s2 s s s2 s2 s s s s s j = k = # of gates = # of gates = s s2 s2 s s s2 s2 s s s s s j = k = # of gates = # of gates = s Total # of gates for J-K flip-flops (on t count z) =

68 ASSIGNMENT #2 Ecitation Table for J-K Flip-Flops Q Q' J K Truth Table: s2 s s s2' s' s' z j2 k2 j k j k

69 Assignment #2: Karnaugh Maps for D Flip-Flops an the output s2 s2 s s s2 s2 s s s s s s s2 = s = # of gates = # of gates = s2 s2 s s s2 s2 s s s s s s s = z = # of gates = # of gates = Total # of gates for D flip-flops (on t count z) =

70 Assignment #2: Karnaugh Maps for J-K Flip-Flops s2 s2 s s s2 s2 s s s s s j2 = k2 = # of gates = # of gates = s s2 s2 s s s2 s2 s s s s s j = k = # of gates = # of gates = s s2 s2 s s s2 s2 s s s s s j = k = # of gates = # of gates = s Total # of gates for J-K flip-flops (on t count z) =