Review for B33DV2Digital Design. Digital Design


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1 Review for B33DV2
2 The Elements of Modern Behaviours Design Representations Blocks Waveforms Gates Truth Tables Boolean Algebra Switches Rapid Prototyping Technologies Circuit Technologies TTL MOS Simulation Synthesis PAL, PLA, ROM, PLD,EPLD,FPGA ComputerAided Design 2
3 Combinational logic Combinational vs. Sequential Logic no feedback among inputs and outputs outputs are a pure function of the inputs e.g., full adder circuit: (A, B, Carry In) mapped into (Sum, Carry Out) A B Cin Full Adder Sum Cout Sequential logic Network implemented from switching elements or logic gates. The presence of feedback distinguishes between sequential and combinational networks External inputs X X2 Switching network Z Z2 outputs Xn Zm feedback Introduces memory 3
4 Sequential logic Sequential Systems network typically has only a limited number of unique configurations these are called states e.g., a simple traffic light controller sequences infinitely through four states outputs depend on inputs and the entire history of execution! output and new state is a function of the inputs and the old state outputs = F(inputs, present_state) includes components to remember the current state i.e., the fed back inputs are the state Synchronous systems internal state changes synchronized to edges of a clock signal effect of changes propagate between clock edges as in a standard Intel PC Propagation time 4
5 Representations used in Boolean algebra Mathematical representation of static binary logic Truth tables Tabular representation of ALL input/output combinations Minterms,(maxterms) Boolean algebra representations of truth tables Logic diagrams Schematic diagram of logic system Timing diagrams Shows timing relationships between system units Karnaugh maps Geometrical representation of truth table data State transition diagrams For sequential systems shows relationship between the states of a system ASM charts For sequential systems shows sequencing between the states of a system 5
6 Rules of Boolean Algebra. Commutative Law A. B = B. A A + B = B + A 2. Associate Law (A. B). C = A. (B. C) (A + B) + C = A + (B + C) 3. Distributive Law (A + B). C = (A. C) + (B. C) (A. B) + C = (A + C). (B + C) 4. Identities 5. A + = A A. = A A + = A. = A + A = A A. A = A A + (A ) = A. (A ) = 8. Inverse (A ) = A 9. De Morgan s Theorem (A+ B) = (A ). (B ) (A. B) = (A ) + (B ) Evaluation order Parentheses (NOT) * (AND) + (OR) 6
7 Truth Table to SOP Form SumfProducts (SOP) form can be written directly from truth table. A B C F F(A,B,C) = A b c + a B C + a B c + a b C + a b c A b c a B C a B c a b C a b c minterms Note that each term has ALL variables present. If a product term has ALL variables present, it is a MINTERM. 7
8 Minterm Notation Each line in a truth table represents a Minterm. Row No. A B C Minterms A B C = m A B c = m 2 A b C = m 2 3 A b c = m 3 4 a B C = m 4 5 a B c = m 5 6 a b C = m 6 7 a b c = m 7 8
9 Logic Functions: From Expressions to Gates More than one way to map an expression to gates T2 E.g., z = (A * (B * (c + d))) = A * B * (c + d) T Implementation Implementation 2 A B Z A B Z C D T 2 T C D 5 gates 4 gates use of 3input gate 9
10 Timing Diagram Notation H L t su tho t H L Changing values Stable Value, high or low Changing values H L Clean transitions H L t skew H L Stable, driven Tristate High impedance
11 Karnaugh Map Method Karnaugh Map Kmap is an alternative method of representing the truth table that helps visualize adjacent terms in up to 6 dimensions 2variable Kmap A B C AB A 6 4 AB CD C A D 3variable Kmap 3 B 7 5 B 4variable Kmap Numbering Scheme:,,, Gray Code only a single bit changes one code word to the next
12 Grouping blocks of Simplification using KMaps A group must consist of 6,8,4,2 or cells Each cell must be horizontally and/or vertically adjacent to cells in the other group Always include the largest number of s in a group Each in the map should be included in a group Groups can overlap Map edge cells connect in a loop to cells at the opposite edge Naming groups The product description for a group will include ALL variables that are CONSTANT over the group For example, for a 4variable map An 8cell group is described by a variable product term An 4cell group is described by a 2variable product term An 2cell group is described by a 3variable product term An cell group is described by a 4variable product term 2
13 Minimal Solution A minimal SOP will consist of prime implicants. A minimal SOP equation will have all of the essential prime implicants on the map. By definition, these cover a minterm that may not be covered by some other prime implicant. The minimal SOP equation may or may not include nonessential prime implicants. It will include nonessential prime implicants if there are s remaining that have not been covered by an essential prime implicant. 3
14 Don t Cares treated as s or s AB CD X X X X X X Treat X s as s to make larger groupings. All X s do not have to be covered. F(A,B,C,D) = cd + Bc 4
15 VariableEntered Karnaugh Maps (VEM) VEM Key idea: Represent values of function in terms of its variables (called mapentered variables) within Karnaugh map framework Group like variables in Karnaugh map cells Minimisation approach Map all s Convert s to X s (i.e. don t cares) Map SIMILAR components 5
16 Hazards in Combinational Circuits AB C AB C f = AB' + BC f = AB' + BC + AC To avoid hazards: every pair of adjacent s should be covered by a group 6
17 FlipFlops/ Latches Latches and FlipFlops are devices that can have two internal states (,) The output of a latch or a FlipFlop (FF) is dependent upon its CURRENT STATE CURRENT INPUTS. Latches and FFs are the simplest examples of sequential systems. State transitions based on levels edges 7
18 Dtype FlipFlop Clocked, edge triggered input present state next state D clock Dtype FF Q Q The next state in response to the rising edge of the clock is equal to the D input before the rising edge 8
19 Clocked JK FlipFlop do nothing reset set toggle negative edge triggered next state JK = => no state change occurs JK = => the flipflop is set to, independent of the current state JK = => the flipflop is always reset to JK = => the flipflop changes the state Q + = Q (toggle) 9
20 Moore machine Sequential System Concepts feedback clock Outputs are only dependent on the state variables inputs Combinatorial logic Excitation variables register State storage Combinatorial logic outputs Mealy machine feedback clock Outputs are dependent on the state variables and the inputs Combinatorial logic Excitation variables register Combinatorial logic inputs outputs 2
21 Self loop The state diagram state FSM Finite State Machine State transition start a Reason for state change State name done start Mealy or conditional output State code d ready b ready [error = state(b) & ready] Moore output c [running] done 2
22 Assignment of state codes The state codes can be allocated in any way, but must adhere to one rule Asynchronous variable rule State variables. There should never be more than 2 states from a state whose branching is controlled by an asynchronous input variable 2. The two next states MUST have logically adjacent states State codes P b DE a P c Asynchronous input E D a d b c d From state a, next states b and c are adjacent. i.e. only differ by D 22
23 Algorithmic State machine (ASM) chart notation Similar to flow charts State Moore output True : Input False : Signal? Defines a single system state with associated Moore outputs Defines the testing of a single binary input signal Mealy output Defines a single transient output 23
24 Algorithmic State machine charts Based on flow charts a start b 2. Draw state diagram ready c d a start ready start ready decision state c ready b ready d rea 24
25 Excitation table for Dtype excitation equations Table of state transitions Code of target state Boolean on transition state transitions A B C DA DB DC a a a a c start b b a c c c wait c d wait wait d d b error d e error e e e pause e f pause pause f f d done done a a Dinput excitation values for state variable A Dtype flipflop 25
26 Excitation table for Dtype excitation equations Transitions table to Karnaugh Map State d Code of target state ns A B C error pause pause Boole BC A DA a b d c error e f pause + pause State e Map rules X X. Map s 2. Convert s to don t cares ( X ) 3. Map LIKE entries Da 26
27 System design Digital system consist of two cooperating units Data Control Data in Data manipulation Control signals control Control signals Data out E.g. A computer, a graphics card, an ethernet interface, etc 27
28 Data manipulation components The components available to the designer include Registers Counters Up, down Shift registers Left, right Multplexors Also called data selectors Demultiplexors Comparators Arithmetic units Adders, subtractors, incrementors, multipliers, ALUs At design time it is important to see these blocks as BLACK BOXES Their individual design can be decided at a later stage Need only define inputs and outputs Direction Polarity Level or edge 28
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58 26 Q Convert the following state diagram into a set of excitation equations for a Dtype implementation. T is a single input variable and each of the 4 states (a to d) has been given an appropriate binary coding. T a T d T b T T c T 58
59 State transition table State Transitions Code of target state Boolean on transition P Q Dp Dq a a a a b T b b b b c T T T c c a c d T d d d Karnaugh maps Q P a b T T d c Dp Q P T Dq Dp = pq + pt + PqT Dq = Pq + Pt 59
60 26 Q2 A long communications channel needs to be tested for potential problems. The technique used is to send a sequence of values through the channel and route them back through a loopback connection. The simplest sequence is to send the numbers,, 2, 3, etc. Each sent value is compared to the received value. Any difference will cause an error counter to be incremented. A test session is to be run for 3 seconds. A timer unit will provide this feature. During a test session, a large number of values will be sent through the channel and compared for errors. The block diagram is as follows counter State Machine clear increment channel go equal = Loopback connector comparator start timecomplete 3 sec Timer clear2 increment2 Error counter 2 Generate a state transition diagram for this system. Using a Moore machine representation, show the outputs as part of the state machine. Hence produce a set of excitation equations for a Dtype flipflop implementation. 6
61 G t a g b [clear, clear2, start] g T e [inc2] c [inc] E d f e 6
62 62 Transition table T g c g a f g e g e E e d e d f c d b c g a a a b Dr Dq Dp R Q P Target state T g c g a f g e g e E e d e d f c d b c g a a a b Dr Dq Dp R Q P Target state
63 PQ R e+e X Dp Dp = pq + qr PQ R T X Dq Dp = PqR + pq + Qr +pt PQ R g Dr = PqR + PRg + qre e X Dr 63
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