Carry Look-ahead Adders. EECS150 - Digital Design Lecture 12 - Combinational Logic & Arithmetic Circuits Part 2. Carry Look-ahead Adders

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1 EECS5 - Digital Design Leture 2 - Combinational Logi & Arithmeti Ciruits Part 2 Otober 3, 22 John Wawrzynek In general, for n-bit addition best we an ahieve is delay α log(n) How do we arrange this? (think trees) First, reformulate basi adder stage: a b i i+ s arry kill k i = b i arry propagate p i = b i arry generate g i = b i i+ = g i + p i i s i = p i i Fall 22 EECS5 - Le2-la2 Page Fall 22 EECS5 - Le2-la2 Page 2 Group propagate and generate signals: p i g i p i+ g i+ p i+k g i+k in P = p i p i+ p i+k G = g i+k + p i+k g i+k- + + (p i+ p i+2 p i+k )g i out a b a b a 2 b 2 a 3 b 3 a 4 b 4 a 5 b 5 a b P a G a 3 = G a + P a P b G b 9-bit Example of hierarhially generated P and G signals: P = P a P b P P true if the group as a whole propagates a arry to out G true if the group as a whole generates a arry Group P and G an be generated hierarhially. C out = G + PC in a 6 b 6 a 7 b 7 a 8 b 8 6 = G b + P b 3 P G 9 = G + P G = G + P G b + P b P G a Fall 22 EECS5 - Le2-la2 Page 3 Fall 22 EECS5 - Le2-la2 Page 4

2 a b s a b s a 2 b 2s2 p,g 2 b isi i i+ p,g p = a b g = ab s = p i i+ = g + i p p P 8 =p p g s p = g +p G 8 =g +p g g s 2 =G 8 +P 8 p 2 P 9 =p 2 p 3 g2 8-bit Carry Look-ahead Adder with 2-input gates. P =P 8 P 9 G =G 9 +P 9 G 8 3 a 3 b 3s3 a 4 b 4s4 5 a 5 b 5s5 a 6 b 6s6 7 a 7 b 7s P a,g a P b,g b 8-bit Carry Lookahead Adder in out P = P a P b G = G b + G a P b C out = G + in P s2 p 3 = g 2 +p 2 2 G 9 =g 3 +p 3 g 2 3 g3 s3 4 p 4 4 P a =p 4 p 5 g4 s4 p 5 = g 4 +p 4 4 G a =g 5 +p 5 g 4 5 g5 s5 6 =G a +P a 4 p 6 6 g6 s6 p 7 = g 6 +p g7 s7 P b =p 6 p 7 G b =g 7 +p 7 g =G +P 8 =G e +P e P d =P a P b G d =G b +P b G a P e =P P d G e =G d +P d G Fall 22 EECS5 - Le2-la2 Page 5 Fall 22 EECS5 - Le2-la2 Page 6 Carry look-ahead Wrap-up Adder delay α log 2 N (up then down the tree). Cost? Can be applied with other tehniques. Group P & G signals an be generated for sub-adders, but another arry propagation tehnique (for instane ripple) used within the group. Other more omplex tehniques exist that an bring the delay down below O(logN), but are only effiient for very wide adders. n-bit shift registers A B reset FF Bit-serial Adder A, B, and R held in shiftregisters. Shift right one per lok yle. Reset is asserted by ontroller. n-bit shift register s R Addition of 2 n-bit numbers: takes n lok yles, uses FF, ell, plus registers the bit streams may ome from or go to other iruits, therefore the registers may be optional. Fall 22 EECS5 - Le2-la2 Page 7 Fall 22 EECS5 - Le2-la2 Page 8

3 Dediated arry logi provides fast arithmeti arry apability for high-speed arithmeti funtions. The Virtex-E CLB supports two separate arry hains, one per Slie. The height of the arry hains is two bits per CLB. The arithmeti logi inludes an XOR gate and AND gate that allows a 2-bit full adder to be implemented within a slie. Cin to Cout delay =.ns, versus.4ns for F to X delay. Adders on the Xilinx Virtex How do we map a 2-bit adder to one slie? Fall 22 EECS5 - Le2-la2 Page 9 Multipliation a 3 a 2 a a Multipliand b 3 b 2 b b Multiplier X a 3 b a 2 b a b a b a 3 b a 2 b a b a b Partial a 3 b 2 a 2 b 2 a b 2 a b 2 produts a 3 b 3 a 2 b 3 a b 3 a b 3... a b +a b a b Produt Many different iruits exist for multipliation. Eah one has a different balane between speed (performane) and amount of logi (ost). Fall 22 EECS5 - Le2-la2 Page + n-bit adder Shift and Add Multiplier P B n-bit shift registers A n-bit register Cost α n, Τ = n lok yles. What is the ritial path for determining the min lok period? Sums eah partial produt, one at a time. In binary, eah partial produt is shifted versions of A or. Control Algorithm:. P, A multipliand, B multiplier 2. If LSB of B== then add A to P else add 3. Shift [P][B] right 4. Repeat steps 2 and 3 n- times. 5. [P][B] has produt. Fall 22 EECS5 - Le2-la2 Page Signed Multipliation: Shift and Add Multiplier Remember for 2 s omplement numbers MSB has negative weight: N 2 i n X = x i 2 xn 2 i= ex: -6 = 2 = = = -6 Therefore for multipliation: a) subtrat final partial produt b) sign-extend partial produts Modifiations to shift & add iruit: a) adder/subtrator b) sign-extender on P shifter register Fall 22 EECS5 - Le2-la2 Page 2

4 b3 b2 b b P7 P6 P5 P4 Array Multiplier Generates all n partial produts simultaneously. a a a2 a3 Fall 22 EECS5 - Le2-la2 Page 3 P P P2 P3 Eah row: n-bit adder with AND gates arry out b j sum in sum out arry in What is the ritial path? Speeding up multipliation is a matter of speeding up the summing of the partial produts. Carry-save addition an help. Carry-save addition passes (saves) the arries to the output, rather than propagating them. Carry-save Addition arry-save add arry-propagate add Example: sum three numbers, 3 =, 2 =, 3 = = 4 s = 3 = 2 s = 6 = 8 arry-save add In general, arry-save addition takes in 3 numbers and produes 2. Whereas, arry-propagate takes 2 and produes. With this tehnique, we an avoid arry propagation until final addition Fall 22 EECS5 - Le2-la2 Page 4 Carry-save Ciruits Array Multiplier using Carry-save Addition b3 b2 b b s s s s s s When adding sets of numbers, arry-save an be used on all but the final sum. Standard adder (arry propagate) is used for final sum. s s x x x 2 a a a2 a3 P P P2 P3 arry out b j sum in sum out arry in CPA Fast arrypropagate adder Fall 22 EECS5 - Le2-la2 Page 5 P7 P6 P5 P4 Fall 22 EECS5 - Le2-la2 Page 6

5 Carry-save Addition is assoiative and ommunitive. For example: (((X + X )+X 2 )+X 3 ) = ((X + X )+(X 2 +X 3 )) x 7 x 6 x 5 x 4 x 3 x 2 x x log 3/2 N A balaned tree an be used to redue the logi delay. This struture is the basis of the Wallae Tree Multiplier. Partial produts are summed with the tree. Fast CPA (ex: CLA) is used for final sum. Multiplier delay α log 3/2 N + log 2 N CPA log 2 N Fall 22 EECS5 - Le2-la2 Page 7