Lecture 2: Computer Arithmetic: Adders

Transcription

1 CMU S 9 L Leture 2: Computer Arithmeti: Adder Jame C. Hoe Dept of ECE, CMU January 4, 29 Announement: No la on Monday Verilog Refreher next Wedneday Review P&H Ch 3 Handout: Lab and HW will be poted on Blakboard thi weekend Binary Number Repreentation CMU S 9 L Let b n- b n-2 b 2 b b repreent an n-bit unigned integer it value i n weight of the i th digit i= 2 i bi value of the i th digit a finite repreentation between and 2 n - e.g., two = 8 ten + 2 ten + ten = ten (more ommonly rewritten =) Often written in Hex for eaier human onumption to onvert, tarting from the LSB, map 4 binary digit at a time into a orreponding hex digit; and vie vera e.g., _ two =AB hex For onverting between binary and deimal, memorize deimal value of 2 ~ 2, and remember 2 i about.

2 CMU S 9 L Complement Number Repreentation Let b n- b n-2 b 2 b b repreent an n-bit igned integer it value i 2 n b n n 2 i= a finite repreentation between -2 n- and 2 n- - e.g., aume 4-bit 2 -omplement b = = -5 b = = - To negate a 2 -omplement number add to the bit-wie omplement aume 4-bit 2 -omplement (- b ) = b + = b = 5 (- b ) = b + = b = -5 (- b ) = b + = b = (- b ) = b + = b = + i 2 b i Intuition: a 4-bit example b =4 b =-2,4 b =5 b =-,5 CMU S 9 L b = (a 2 ), unigned) (a unigned) b =, b =2,2 b =3 b =-3,3 b =2 b =-4,2 b = b =-5, b = b =-6, 4-bit 6 value (whether igned or unigned) b =3,3 b =4,4 b =5,5 b =6,6 how to add two number b =9 b =-7,9 b =7,7 b =8 b =-8,8 what it mean to overflow the number repreentation how to negate a number Ye, i a poitive number in CS

3 Smaller to Larger Binary Repreentation Unigned number pad the left with a many a you need (aka -extenion) e.g. 4 b 8 b_ 2 -omplement number poitive: pad the left with a many a you need negative: pad the left with a many a you need e.g. 4b 8 b_ 4b 8 b_ or generially, pad the left with the ame value a the original ign-bit a many time a neeary (aka ignedextenion) CMU S 9 L What about onverting from larger to maller repreentation? (Unigned) Binary Addition CMU S 9 L Long Hand b 3 a 3 b 2 a 2 b a b a 4 arry? What about ubtration?

4 Full Adder CMU S 9 L out FA a b out = a b out = b +a +ab 3-way majority parity a, b, are funtionally inditinguihable a input Unigned Binary Addition CMU S 9 L b 3 a 3 b 2 a 2 b a b a 4 4 overflow? arry? o i o i 3 2 o i o i 3 2 Could ue a half-adder, but let wait

5 2 -Complement Addition CMU S 9 L b 3 a 3 b 2 a 2 b a b a 4 arry? o i o i o i o i 3 2 overflow? = (a 3 b 3 )? : (a 3 3 ) - an t overflow when adding a po. and a neg. number - if 2 po. number yield a neg. number V; vie 2 -Complement Subtration CMU S 9 L2-29 Subtrating i like adding the negative Negation i eay in a 2 -omplement repreentation A B bit-wie omplement v ub? S How do you build a omparator (i.e., >, <)?

6 Analyi of an n-bit Ripple-Carry Adder Size/Complexity: O(n) n x SizeOf( Full Adder ) CMU S 9 L2-29 Critial Path Delay: O(n) n x DelayOf( Full Adder ) n x 2 gate delay (auming 2-level SOP i ued) b n- a n- b a b a ab ab ab out o i o i o i n- Global Clok Simplified Timing lok period hoen to be greater than wort-ae T pd CMU S 9 L Syn omb omb Syn Syn omb omb Syn Syn omb omb Syn regiter lath new value T pd : ombinational propagation delay No more hange to Q What about etup-time, hold-time, kew and uh?

7 High-Performane Adder? CMU S 9 L Intel P4 i deigned around a lok period that i twie the 6-bit adder lateny Uing a rough etimation gate delay.5 n-per-miron x feature-ize a 9nm proe ha gate delay = 45p If Intel ued a ripple-arry adder then P4 hould be running ~ / (2x2x6x45p) = 347MHz Alternatively peaking, 3GHz P4 would have to add 2 6-bit number in ~4 gate delay Cutting Down the Carry Chain How to redue the arry-propagation delay? Remember, long-hand i how mot of u add, but not the only way Can we ompute an intermediate arry ignal without firt omputing the earlier one e.g., let m (or m ) be a funtion of a m...a and b m...b 2 =(a a b )+(a a )+(a b )+(b a b )+(b a ) +(b b )+(a b ) Complexity grow exponentially in n exponential in t too bad for mall n gate delay i 2, independent of n b n- a n- b a true for mall n CMU S 9 L b a What about large n? n- n-

8 Carry-Selet Adder CMU S 9 L A 5:8 B 5:8 A 7: B 7: adder 8 adder 8 adder 8 S 7: C S 5:8 3 adder operate in parallel!! ot=.5 n FA ize + mux delay=.5 n FA delay +mux-delay if n=6 ~6 gate-delay Multi-Stage CSA CMU S 9 L a 5:2 b 5:2 a :8 b :8 a 7:4 b 7:4 a 3: b 3: adder 4 adder 4 adder 4 adder 4 5:2 :8 7:4 3: ot=(2k-)/k n FA ize + mux --- for k-tage delay=n FA delay /k +(k-) mux-delay k=4,n=6 ~8 gate-delay + 3 mux-delay k=8,n=6 ~4 gate-delay + 7 mux-delay k=6,n=6 ~2 gate-delay + 5 mux-delay

9 Variable-Length CSA CMU S 9 L a 5: b 5: a 9:5 b 9:5 a 4:2 b 4:2 a b a b adder 6 adder 5 adder 3 FA FA 5: 9:5 4:2 -double the ot -delay et by the longet adder tage, grow by O(n /2 ) with areful ritial path tuning Can we have ut-down the arrie without 2x ot? Carry Generate and Propagate CMU S 9 L a b out out X X If a b then out i regardle of (arry generate) if a b then out i the ame a (arry propagate) g i =a i b i p i =a i b i loal deiion baed on a i and b i only

10 Small Carry-Look-Ahead Adder CMU S 9 L Given g i =a i b i p i =a i b i i+ = g i + (p i i ) Thu =g +(p ) 2 =g +(p )=g +(p (g +(p )))=g +p g +p p 3 =g 2 +p 2 g +p 2 p g +p 2 p p 4 =g 3 +p 3 g 2 +p 3 p 2 g +p 3 p 2 p g +p 3 p 2 p p and o on -We an ompute n in O(log n) gate delay and O(n 2 ) ize, only manageable for mall n -Given n we an ompute n for a ontant additional delay Prefix Carry-Look-Ahead CMU S 9 L Given =g +(p ) 2 =g +(p )=g +(p (g +(p )))=g +p g +p p 3 =g 2 +p 2 g +p 2 p g +p 2 p p 4 =g 3 +p 3 g 2 +p 3 p 2 g +p 3 p 2 p g +p 3 p 2 p p A a 4-arity group G4=g 3 +p 3 g 2 +p 3 p 2 g +p 3 p 2 p g G P P4=p 3 p 2 p p g n-: p n-: CLAn Pn Gn

11 Prefix Carry-Look-Ahead CMU S 9 L p [5:2] g [5:2] [5:2] p [:8] g [:8] [:8] p [7:4] g [7:4] [7:4] p [3:] g [3:] [3:] CLA 4 CLA 4 CLA 4 CLA 4 G 3 P 3 Cin 6 G 2 P 2 Cin 8 G P Cin 4 G P Cin CLA 4 CLA 6 G6 Cin P6 Thi truture an be reured: O(log n) delay, O(n) ize Computing Individual Carrie CMU S 9 L Example: 8-bit, 2-ary CLA g p g p g 2 p 2 g 3 p 3 = generate for bit ~ = Cin = g + p Cin 2 = G + P Cin 4 = G3 + P3 Cin C out = G7 + P7 Cin G7 g 4 p 4 g 5 p 5 g 6 p 6 g 7 p 7 P7 3 = g 2 + p = g 4 + p = G54 + P = g 6 +p 6 (G54 + P54 4 )

12 Large Adder uing Carry-Skip CMU S 9 L A IV A IV A III B III A II B II A I B I P G+P G CLA n/4 P G+P G CLA n/4 P G+P G CLA n/4 P G+P G CLA n/4 adder n/4 adder n/4 adder n/4 adder n/4 out S IV S III S II S I Fat enough and heaper than omputing individual i by G.P. Adder at a Glane CMU S 9 L Ripple Adder O(n) ize, O(n) delay Carry-Selet Adder O(n) ize, O(n.5 ) delay Carry-Look-Ahead Adder O(n 2 ) ize, O(log n) delay Prefix Adder O(n) ize, O(log n) delay But, remember all approahe have deign weetpot and make different tradeoff There alo are iruit-level adder trik (e.g., Manheter arry hain)

13 Blak Magi of Adder Deign CMU S 9 L High-performane adder deign are extremely important to high-performane omputing Studied extenively in theoretial framework Worked on extenively in pratie Neverthele remain very muh a trial-and-error deign exerie For a 64-bit adder, one might ontrut adder of variou (hort) length uing 2-level logi a 6-bit adder from mall adder with variable-length arry-elet a 32-bit adder from 2 6-bit CSA with CLA to determine arry for the upper 6 bit a 64-bit 2-tage CSA adder from 3 32-bit adder