Arithmetic Circuits. Comp 120, Spring 05 2/10 Lecture. Today s BIG Picture Reading: Study Chapter 3. (Chapter 4 in old book)

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1 omp 2, pring 5 2/ Leture page Arithmeti iruits Didn t I learn how to do addition in the seond grade? UN ourses aren t what they used to be... + Finally; time to build some serious funtional bloks We ll need a lot of boxes Reading: tudy hapter 3. (hapter 4 in old book) omp 2 pring 25 2//5 L9 Arithmeti iruits Today s BIG Piture Thus far, we ve been designing in the small, onentrating on tehnique, rather than the design of useful systems. Today, we make a HUGE leap to designing in the large. Our fous will be on designing ombinational logi with so many inputs and outputs that they would be impratial to design using the logi optimization tehniques we ve disussed previously. These proessing bloks are also impratial to implement using regular logi strutures suh as ROMs or PLAs. Many of these bloks hinge on lever triks that have withstood the test of time. omp 2 pring 25 2//5 L9 Arithmeti iruits 2

2 omp 2, pring 5 2/ Leture page 2 Review: 2 s omplement N bits -2 2 N- N sign bit Range: 2 N- to 2 N- binary point 8-bit 2 s omplement example: = = = 42 If we use a two s-omplement representation for signed integers, the same binary addition proedure will work for adding both signed and unsigned numbers. By moving the impliit binary point, we an represent frations too:. = = = omp 2 pring 25 2//5 L9 Arithmeti iruits 3 Binary Addition Here s an example of binary addition as one might do it by hand : Adding two N-bit numbers produes an (N+)-bit result + arries from previous olumn We ve already built the iruit that implements one olumn: O I o we an quikly build a iruit to add two 4-bit numbers A3 B3 A2 B2 4 3 omp 2 pring 25 2//5 L9 Arithmeti iruits 4

3 omp 2, pring 5 2/ Leture page 3 ubtration: A-B = A + (-B) Using 2 s omplement representation: B = ~B + ~ = bit-wise omplement B B B B o let s build an arithmeti unit that does both addition and subtration. Operation seleted by ontrol input: B3 B2 B B ubtrat A3 A2 A A But what about the +? 4 3 omp 2 pring 25 2//5 L9 Arithmeti iruits 5 ondition odes Besides the sum, one often wants four other bits of information from an arithmeti unit: Z (zero): result is = N (negative): result is < N- big NOR gate (arry): indiates that add in the most signifiant position produed a arry, e.g., + (-) from last FA V (overflow): indiates that the answer has too many bits to be represented orretly by the result width, e.g., (2 i- - )+ (2 i- -) V = N + N i i i i -or- V = O I i i omp 2 pring 25 2//5 To To ompare A and and B, B, perform perform A B A B and and use use ondition odes: odes: igned igned omparison: LT LT N V N V LE LE Z+(N V) EQ EQ Z NE NE ~Z ~Z GE GE ~(N V) GT GT ~(Z+(N V)) Unsigned omparison: LTU LTU LEU LEU +Z +Z GEU GEU ~ ~ GTU GTU ~(+Z) L9 Arithmeti iruits 6

4 omp 2, pring 5 2/ Leture page 4 T PD of Ripple-arry Adder A n- B n- A n-2 B n-2 A 2 B 2 A B A B n- n-2 2 Worse-ase path: arry propagation from LB to MB, e.g., when adding to. t PD = (t PD,XOR +t PD,OR + t PD,AND ) +(N-2)*(t PD,OR + t PD,AND ) + t PD,XOR Θ(N) XOR(A,B) to O I to O I N- to N- Θ(N) is read order N and tells us that the lateny of our adder grows in proportion to the number of bits in the operands. O I omp 2 pring 25 2//5 L9 Arithmeti iruits 7 Faster arry Logi Let s see if we an improve the speed by rewriting the equations for OUT : OUT = AB + A IN + B IN = AB + (A + B) IN = G + P IN where G = AB and P = A + B generate propagate For adding two N-bit numbers: N = G N- + P N- N- = G N- + P N- G N-2 + P N- P N-2 N-2 Atually, Atually, P P is is usually usually defined defined as as P P = A B A B whih whih won t won t hange hange OUT but OUT but will will allow allow us us to to express express as as aa simple simple funtion funtion of of P P and and IN : IN : = P P IN IN = G N- + P N- G N-2 + P N- P N-2 G N P N-...P IN N in only 3 (!) gate delays: for P/G generation, for ANDs, for final OR O G P I omp 2 pring 25 2//5 L9 Arithmeti iruits 8

5 omp 2, pring 5 2/ Leture page 5 N-Bit Addition in onstant Time? o if we had (N+)-input gates and didn t mind a lot of loading on the P signals, the propagation delay of adder built using P/G equation to ompute IN of eah bit would be: 4 gate delays Θ() Of ourse, this is impratial when N is large (i.e. > 4) but it does lead to some interesting ideas: faster ripple-arry implementations hierarhial arry-lookahead adders omp 2 pring 25 2//5 L9 Arithmeti iruits 9 arry-lookahead Adders (LA) We an build a hierarhial arry hain by generalizing our definition of the arry Generate/Propagate (GP) Logi. We start by dividing our addend into two parts, a higher part, H, and a lower part, L. The GP funtion an be expressed as follows: Generate a arry out if the high part generates one, G HL = G H + P H G L or if the low part generates one and the high part propagates it. Propagate a arry if both the high P HL = P H P L and low parts propagate theirs. G H P H GP G L P L P/G generation O FA I G P O FA I G P G HL P HL Hierarhial building blok st level of lookahead G H P H GP G L P L G HL P HL omp 2 pring 25 2//5 L9 Arithmeti iruits

6 omp 2, pring 5 2/ Leture page 6 8-bit LA (GP Generation) A7 B7 A6 B6 A5 B5 A4 B4 A3 B3 A2 B2 G P G P G P G P G P G P G P G P G H P H G L GP G HL P HL P L G H P H G L GP G HL P HL P L G H P H G L GP G HL P HL P L G H P H G L GP G HL P HL P L G 7-6 P 7-6 G 5-4 P 5-4 G 3-2 P 3-2 G - P - Log 2 (N) G H P H G L GP G HL P HL P L G H P H G L GP G HL P HL P L G 7-4 P 7-4 G 3- P 3- G H P H G L GP G HL P HL P L G 7- P 7- We an build a tree of GP units to ompute the generate and propagate logi for any sized adder. For a 2 N -bit adder, we need 2 N - GP units. = G 7 + P 7 G 6 + P 7 P 6 G 5 + P 7 P 6 P 5 G P 7...P IN G 7- P 7- omp 2 pring 25 2//5 L9 Arithmeti iruits 8-bit LA (arry Generation) Now, given a the value of the arry-in of the least-signifiant bit,we an generate the arries for every adder. j = G + P i Log 2 (N) G 6 G j G 4 G j G 2 G j G P i P i P i 6 P 4 i P 2 P i P i G 5-4 P 5-4 G 3- P 3- G j P i 4 G j P i i G j P i i G j P i i G - i P - Notie that the inputs on the right of eah bloks are the same as the inputs on the left of eah orresponding GP blok. omp 2 pring 25 2//5 L9 Arithmeti iruits 2

7 omp 2, pring 5 2/ Leture page 7 8-Bit LA (omplete) A 7 B 7 A 6 B 6 A 5 B 5 A 4 B 4 A 3 B 3 A 2 B 2 A B A B G P G P G P G P G P G P G P G P G H P H j G L GP/ P L G H P H j G L GP/ P L G H P H j G L GP/ P L G H P H j G L GP/ P L G i HL P HL i G i HL P HL i G i HL P HL i G i HL P HL i G H P H j G L GP/ P L G H P H j G L GP/ P L G i HL P HL i G i HL P HL i G H P H j G L GP/ P L G i HL P HL i t PD = Θ(log(N)) G H P H GP G L G HL P HL P L + G j L P L i i = G H P H j GP/ G L P L G HL P HL i I Notie that we don t need the arry-out output of the adder any more. O I G P omp 2 pring 25 2//5 L9 Arithmeti iruits 3 arry-kip Adders Idea: full P/G equations are ompliated, but P by itself is simple. o just use P to skip arry aross a blok of ripple-arry adders: A B K-bit bloks (K=4 in figure) (A) arries ripple simultaneously through eah blok; if blok generates a arry, it appears on arry-out of blok (similar to G). If arry-in is at start of operation, no spurious arry-outs will be generated. (B) If arry-in and P BLOK are both true, arry skips to next blok () arry ripples though final blok. t PD = 2*[K+ (N/K 2) + K] With variable size bloks t PD Θ(sqrt(N)) omp 2 pring 25 2//5 L9 Arithmeti iruits 4

8 omp 2, pring 5 2/ Leture page 8 arry-elet Adders Idea: do two additions, one assuming arry-in is, the other assuming arry-in is. Use MUX to selet orret answer when orret arry-in is known. Left bloks an be bigger more ripple time time while waiting for selet With one stage: 5% more ost, but twie as fast as ripple-arry With multiple (variable-size) bloks: t PD Θ(sqrt(N)) omp 2 pring 25 2//5 L9 Arithmeti iruits 5 Adder ummary Adding is not only a ommon, but it is also tends to be one of the most timeritial of operations. As a result, a wide range of adder arhitetures have been developed that allow a designer to tradeoff omplexity (in terms of the number of gates) for performane. maller / lower Bigger / Faster Ripple arry arry kip arry elet arry Lookahead A this point we ll define a high-level funtional unit for an adder, and speify the details of the implementation as neessary. Add sub Add/ub omp 2 pring 25 2//5 L9 Arithmeti iruits 6

9 omp 2, pring 5 2/ Leture page 9 hifting Logi hifting is a ommon operation that is applied to groups of bits. hifting an be used for alignment, as well as for arithmeti operations. X << is approx the same as 2*X X >> an be the same as X/2 For example: X = 2 = 2 X 7 X 6 X 5 X 4 X 3 R 7 R 6 R 5 R 4 R 3 Left hift: (X << ) = 2 = 4 Right hift: (X >> ) = 2 = igned or Arithmeti Right hift: (-X >> ) = ( 2 >> ) = 2 = - X 2 X X HL R 2 R R omp 2 pring 25 2//5 L9 Arithmeti iruits 7 More hifting X 7 X 6 X 5 X 4 X 3 X 2 X X R 7 R 6 R 5 R 4 R 3 R 2 R R X 7 X 6 X 5 X 4 X 3 X 2 X X Using the same basi idea we an build left shifters of arbitrary sizes using muxes. Eah shift amount requires its own set of muxes. Hum, maybe we ould do something more lever. X 7 X 6 X 5 X 4 X 3 X 2 X X HL HL2 HL3 omp 2 pring 25 2//5 L9 Arithmeti iruits 8

10 omp 2, pring 5 2/ Leture page Barrel hifting X 7 X 6 X 5 X 4 X 3 X 2 X X HL R 7 R 6 R 5 R 4 R 3 R 2 R R HL HL4 T 7 T 6 T 5 T 4 T 3 T 2 T T If we onnet our shift-lefttwo shifter to the output of our shift-left-one we an shift by,, 2, or 3 bits. And, if we add one more shiftleft-4 shifter we an do any shift up to 7 bits! o, let s put a box around it and all it a new funtional blok. log 2 (N) bits A Left Barrel hifter Y N-bits N-bits omp 2 pring 25 2//5 L9 Arithmeti iruits 9 Barrel hifting with a Twist At this point it would be straightforward to onstrut a Right barrel shifter unit. However, a simple trik that enables a left shifter to do both. A A 7 A A 6 A 2 A 5 A 3 A 4 A 4 A 3 A 5 A 2 A 6 A A 7 A RGT A 7- HFT RGT Left Barrel hifter Y Y 7 Y Y 6 Y 2 Y 5 Y 3 Y 4 Y 4 Y 3 Y 5 Y 2 Y 6 Y Y 7 Y Y 7- Z 7 Z 6 Z 5 Z 4 Z 3 Z 2 Z Z omp 2 pring 25 2//5 L9 Arithmeti iruits 2

11 omp 2, pring 5 2/ Leture page Boolean Operations It will also be useful to perform logial operations on groups of bits. Whih ones? ANDing is useful for masking off groups of bits. ex. & = (mask selets last 4 bits) ANDing is also useful for learing groups of bits. ex. & = ( s lear first 4 bits) ORing is useful for setting groups of bits. ex. = ( s set last 4 bits) XORing is useful for omplementing groups of bits. ex. ^ = ( s omplement last 4 bits) NORing is useful.. Uhm, beause John Hennessy says it is! ex. # = ( s omplement, s lear) omp 2 pring 25 2//5 L9 Arithmeti iruits 2 Boolean Unit (The book s way) It is simple to build up a Boolean unit using primitive gates and a mux to selet the funtion. ine there is no interonnetion between bits, this unit an be simply repliated at eah position. The ost is about 7 gates per bit. One for eah primitive funtion, A i B i and approx 3 for the Bool 4-input mux. This is a straightforward, but not too elegant of a design. Q i omp 2 pring 25 2//5 L9 Arithmeti iruits 22

12 omp 2, pring 5 2/ Leture page 2 ooler Bools We an better leverage a mux s apabilities in our Boolean unit design, by onneting the bits to the selet lines. Why is this better? ) While it might take a little logi to deode the truth table inputs, you only have to do it one, independent of the number of bits. 2) It is trivial to extend this module to support any 2-bit logial funtion. (How about NAND, John? Atually A & /B might be more useful) NOR OR XOR OR XOR A i, B i Q i bool AND OR Whih ever way makes the most sense to you. Let s get a box around it! A B Boolean Q I m starting to think this guy dreams about muxes omp 2 pring 25 2//5 L9 Arithmeti iruits 23 An ALU, at Last Now we re ready for a big one! An Arithmeti Logi Unit. A B That s a lot of stuff ub Bool Add/ub Bidiretional Barrel hifter Boolean hft Math Flags V, N Flag omp 2 pring 25 2//5 R Z Flag L9 Arithmeti iruits 24

13 omp 2, pring 5 2/ Leture page 3 Did We Forget omething? Even rabbits know how to multiply But, it is a huge step in terms of logi Inluding a multiplier unit in an ALU an potentially double the number of gates used. A good (ompat and high performane) multiplier an also be triky to design. Here we will give an overview of some of the triks used. omp 2 pring 25 2//5 L9 Arithmeti iruits 25 Hey, that looks like an and gate The Binary Multipliation Table X Multipliation Binary multipliation is implemented using the same basi longhand algorithm that you learned in grade shool. x A 2 B 2 A B A A 3 B B 3 AB i alled a partial produt A 3 B A 3 B A 2 B A B A 2 B A B A B A B 2 + A 3 B 3 A 3 B 2 A 2 B 2 A B 2 A 2 B 3 A B 3 A B 3 Multiplying N-digit number by M-digit number gives (N+M)-digit result Easy part: forming partial produts (just an AND gate sine B I is either or ) Hard part: adding M N-bit partial produts omp 2 pring 25 2//5 L9 Arithmeti iruits 26

14 omp 2, pring 5 2/ Leture page 4 equential Multiplier Assume the multipliand (A) has N bits and the multiplier (B) has M bits. If we only want to invest in a single N-bit adder, we an build a sequential iruit that proesses a single partial produt at a time and then yle the iruit M times: N P N- N B M bits + LB N+ N xn A N Init: P, load A&B Repeat M times { P P + (B LB ==? A : ) shift P/B right one bit } Done: (N+M)-bit result in P/B omp 2 pring 25 2//5 L9 Arithmeti iruits 27 imple ombinational Multiplier t PD = * t PD,FA not 6 omponents N * HA N(N-) * FA The Logi of a Half- Adder O NB: this iruit only works for nonnegative operands omp 2 pring 25 2//5 L9 Arithmeti iruits 28

15 omp 2, pring 5 2/ Leture page 5 arry-ave ombinational Multiplier Observation: Rather than propagating the sums aross eah row, the arries an instead be forwarded onto the next olumn of the following row t PD = 8 * t PD,FA omponents 2N * HA N(N-) * FA This small improvement in performane hardly seems worth the effort, however, this design is easier to pipeline. omp 2 pring 25 2//5 L9 Arithmeti iruits 29 Pipelined Multiplier arry save onfiguration t PD = Θ(log(N)) assuming LA as final stage NB: this iruit only works for nonnegative operands omp 2 pring 25 2//5 L9 Arithmeti iruits 3

16 omp 2, pring 5 2/ Leture page 6 Higher-Radix Multipliation Idea: If we ould use, say, 2 bits of the multiplier in generating eah partial produt we would halve the number of olumns and halve the lateny of the multiplier! A N- A N-2 A 4 A 3 A 2 A A x B M- B M-2 B 3 B 2 B B M/ Booth s insight: rewrite 2*A and 3*A ases, leave 4A for next partial produt to do! B K+,K *A = *A = *A A = 2*A 2A or 4A 2A = 3*A 4A A omp 2 pring 25 2//5 L9 Arithmeti iruits 3 Booth Reoding urrent bit pair -89 =. = - * 2 (-) + 2 * 2 2 (8) + (-2) * 2 4 (-32) + (-) * 2 6 (-64) -89 Hey, isn t that a negative number? B 2K+ B 2K B 2K- from previous bit pair ation add add A add A add 2*A sub 2*A sub A sub A add -2*A+A -A+A A in this bit means the previous stage needed to add 4*A. ine this stage is shifted by 2 bits with respet to the previous stage, adding 4*A in the previous stage is like adding A in this stage! Eah bit an be onsidered to have the following weights: W(B 2K+ ) = 2 W(B 2K ) = - W(B 2K- ) = - omp 2 pring 25 2//5 L9 Arithmeti iruits 32

17 omp 2, pring 5 2/ Leture page 7 Booth Reoding Logi surrounding eah basi adder: A i A i- x2 ub - ontrol lines (x2, ub, Zero) are shared aross eah row - Must handle the + when ub is (extra half adders in a arry save array) Zero NOTE: - Booth reoding an be used to implement signed multipliations omp 2 pring 25 2//5 B 2K+ B 2K B 2K- x2 ub Zero X X X X L9 Arithmeti iruits 33 Finally, it s tarting to Look Like a omputer 2. If you arrive at the quiz in a metastable state what is the probability you will resolve into a valid state before the quiz onludes? A. All of the above B. None of the below. All of the above D. One of the above E. None of the above F. None of the above Good luk on next week s quizz! I knew there would be logi on this quiz, but this is not what I expeted. omp 2 pring 25 2//5 L9 Arithmeti iruits 34