THRESHOLD LOGIC. María J. Avedillo, José M. Quintana, and Adoración Rueda

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1 THRESHOLD LOGIC María J. Avedillo, José M. Quintana, and Adoraión Rueda Instituto de Miroeletrónia de Sevilla - Centro Naional de Miroeletrónia Avda. Reina Meredes s/n, (Edif. CICA) E-402, Sevilla, Spain Published at the Enylopedia of Eletrial and Eletronis Engineering", John Webster (Ed.) 999, John Wiley & Sons. Vol. 22, pp Wiley. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for reating new olletive works for resale or redistribution to servers or lists, or to reuse any opyrighted omponent of this work in other works must be obtained from Wiley. This material is presented to ensure timely dissemination of sholarly and tehnial work. Copyright and all rights therein are retained by authors or by other opyright holders. All persons opying this information are expeted to adhere to the terms and onstraints invoked by eah author s opyright. In most ases, these works may not be reposted without the expliit permission of the opyright holder.

2 2 Threshold gates are based on the alled majority or threshold deision priniple, whih means that the output value depends on whether the arithmeti sum of values of its inputs exeeds a threshold. The threshold priniple is general itself and onventional simple logi gates, suh as AND and OR gates, are speial ases of threshold gates. Thus, threshold logi an treat onventional gates as well as threshold gates in general, in a unified manner. For many years logi iruit design based on threshold gates has been onsidered an alternative to the traditional logi gate design proedure. The power of the threshold gate design style lies in the intrinsi omplex funtions implemented by suh gates, whih allow system realizations that require less threshold gates or gate levels than a design with standard logi gates. More reently, there is an inreasing interest in threshold logi beause a number of theoretial results show that polynomial size, bounded level networks of threshold gates an implement funtions that require unbounded level networks of standard logi gates. In partiular, important funtions like multiple-addition, multipliation, division, or sorting an be implemented by polynomialsize threshold iruits of small onstant depth. Threshold gate networks have been found also useful in modelling nerve nets and brain organization, and with variable threshold (or weights) values they have been used to model learning systems, adaptive systems, self-repairing systems, pattern reognition systems, et. Also, the study of algorithms for the synthesis of threshold gate networks is important in areas suh as artifiial neural networks and mahine learning. The artile has three well differentiated setions. First, a basi setion deals with definitions, basi properties, identifiation and CMOS implementation of threshold gates. The seond setion is dediated to the synthesis of threshold gates networks, from those for speifi (and very well studied) funtions suh as symmetri or arithmeti funtions to general proedures for generi funtions. Finally, the third setion desribes the speifi appliation of threshold logi for the analysis and implementation of median and stak filters.

3 3 Threshold and Majority Gates A threshold gate (TG) is defined as a logi gate with n input variables, x i, ( i =,, n), whih an take values 0,, and for whih there is a set of (n+) real numbers w, w 2,, w n, and T, alled weights and threshold respetively, suh that the output of the gate is: f = for w i x i T i = n 0 for w i x i < T n i = () A funtion represented by the output of a threshold gate, denoted by f ( x,,, ), is alled a threshold funtion. The set of weights and threshold an be denoted in a more ompat vetor notation way by [ w, w 2,, w n ; T ]. A majority gate is defined as a logi gate with n input variables, ξ i, ( i =,, n), and a onstant input ξ 0, whih an take values +,, and for whih there is a set of real numbers w 0, w,, alled weights, suh that the output of the gate is: w 2,, w n f = + for w i ξ i 0 i = 0 n for w i ξ i < 0 n i = 0 (2) A funtion represented by the output of a majority gate, denoted by f ( ξ, ξ 2, ξ, n ), is alled a majority funtion. Analogously to the threshold funtion, a majority funtion an be denoted in a vetor notation as [ w, w 2,, w n ; w 0 ξ 0 ].

4 4 Definitions for threshold and majority gates an be seen as different but if + and in a majority gate are orrelated to and 0 in a threshold gate, respetively, then a majority gate with a struture [ w, w 2,, w n ; w 0 ξ 0 ] and a threshold gate [ w, w 2,, w n ; T ] have idential logial operations supposed that the relation ξ i = 2x i is employed and that T is given by: T = n -- w. As a orollary to the above statement, it an be easily shown that the 2 i w 0 ξ 0 i = lass of all threshold funtions is equivalent to the lass of all majority funtions. Heneforth, we will not differentiate between a majority funtion and a threshold funtion as far as logial operations are onerned. For example, the TG defined as [ 23,, ; ] represents the logial funtion f ( x,, x 3 ) = x + x x 3. This swithing funtion an be equally represented as the majority gate [ 2,, ; 2] supposed that binary values + and are orrelated to and 0, respetively. Beause the definition of a threshold funtion is in terms of linear inequalities, threshold funtions are often alled linearly separable funtions. From a geometrial point of view, a TG with n inputs an be seen as a hyperplane utting the boolean n-ube. It evaluates a funtion f in the sense that f ( ) lies on one side of the plane, and f ( 0) on the other. An example is shown in Figure. Figure 2a shows the IEEE standard symbol for a TG with all input weights equal to and threshold in T. This standard does not have any symbol for a TG with weights other than. It is lear that a symbol for that gate an be built by tying together several inputs (a weight of w i for the

5 5 input x i an be obtained by onneting x i to w i gate inputs) but it an result in a umbersome symbol, so we will use the non-standard symbol of Figure 2b for TGs with generi weights. Basi Useful Properties of Threshold Funtions There are a number of properties of threshold funtions whih are useful from the point of view of the viability and effiieny of implementing system using TGs as building bloks. These properties are not proven here but interested readers an find a omplete treatment in Refs. -3. The emphasis here is put on their above mentioned usefulness. Some previous definitions are required. A funtion f(x,,, )ispositive in x i if and only if there is a sum-of-produt expression for f in whih x i does not appear. It an be shown that if f is positive in x i, then whatever the x i - residue of f, f xi ( x,,, ) = f ( x,,, x i =0,, ), is, the x i -residue of f, f xi ( x,,, ) = f ( x,,, x i =,, ), is also. This is, f xi ( x,,, ) implies f xi ( x,,, ), or f xi f xi, where is the symbol for logial impliation. A funtion f ( x,,, ) is negative in x i if and only if there is a sum-of-produt expression for f in whih x i does not appear. It an also be shown that f is negative in x i if and only if f xi f xi. A funtion is unate if and only if it is negative or positive in eah of its variables. Now let us enuniate some properties of threshold funtions:

6 6 Property ) All threshold funtions are unate. There are many unate funtions whih are not threshold funtions. Property 2) The weights assoiated to variables in whih the funtion is positive (negative) are positive (negative). Property 3) Any threshold funtion an be realized with integer weight and threshold values. Property 4) Any threshold funtion an be realized with positive weight and threshold values if inversion is available. The first two properties are important for the implementation of a proedure for identifying threshold funtions, an essential task when a threshold-gate design style is adopted. Determining whether a funtion is unate or not is simpler than determining whether it an be realized by a TG. So first the funtion is heked for unateness. If it is not a unate funtion then it is not a threshold funtion either. Moreover, during the heking for unateness, variables are lassified into positive or negative variables whih also ontributes to the simplifiation of the identifiation proedure applying the seond property. The third and fourth properties are interesting from the point of view of the physial implementation of the TGs. For example, some of the urrently available realizations whih will be desribed later realize positive weights and thresholds. Property 4 guarantees that this do not limit the lass of threshold funtions they an implement. Figure 3 shows the elementary relations of threshold funtions. The meaning of the arrow labelled with is that if f ( x,,, ) is a threshold funtion defined by [w, w 2,,w n ; T], then its omplement f ( x,,, ), is also a threshold funtion defined by [-w,-w 2,,-w n ;-T]. If a funtion an be realized as a threshold element, then seletively omplementing the inputs, it is possible to

7 7 obtain a realization by an element with only positive weights. Threshold Funtion Identifiation An straightforward approah to solve the threshold funtion identifiation problem onsists in writing a set of inequalities from the truth table and solving it. If there exists any solution, the funtion is a threshold funtion with weights and threshold given by the solution. If there is no solution, the funtion is not a threshold funtion. In Figure 4 a pair of examples of this proedure are shown. This proedure is not very effiient beause 2 n inequalities are required for a funtion with n variables. The problem an be solved in a more pratial manner using some of the properties listed above. In order to desribe this alternative proedure some definitions are needed. There are 2 n assignments of values to n boolean variables. An assignment A = ( a, a 2,, a n ) is small than or equal to an assignment B = ( b, b 2,, b n ), denoted as A B, if and only if a i, ( i = 2,,, n). Given a set of assignments {A, A 2,..., A k }, those A i for whih there is b i A j A i not A j suh that, j k, j i, are the maximal assignments. The minimal assignments are those A i for whih there is not A j suh that, j k, j i. Given a funtion depending on n variables, eah assignment for whih the funtion evaluated to is alled a true assignment and eah one for whih the funtion is 0 is alled a false assignment. A j A i The proedure has the following steps:.- Determine whether the funtion f is unate. If not, the funtion is not a threshold funtion and the proedure finishes.

8 8 2.- Convert the funtion, f, into another one, g, positive in all its variables by omplementing every variable for whih f is negative. 3.- Find minimal true assignments and maximal false assignments for g. 4.- Generate inequalities for the assignment obtained in step three. If there is no solution to suh set of inequalities the funtion g is not threshold and the proedure finishes. 5.- Derive weights and threshold vetor for original funtion f applying above stated properties. For every variable, x i, whih is omplemented in the original funtion, its assoiated weight is hanged to -w i, and T to T -w i. Figure 5 illustrates the proedure for funtions h and f from Figure 4. CMOS Threshold Gate Implementations Effetiveness of threshold logi as an alternative for modern VLSI design is determined by the availability, ost and apabilities of the basi building bloks. In this sense, several interesting iruit onepts have been explored reently for developing standard-cmos ompatible threshold gates. The most promising are presented in this setion. In order to denote their ontext of appliation, we distinguish between stati and dynami realizations. a) Stati threshold-logi gates There are two notable ontributions to stati threshold gate CMOS implementations: one is based on the ganged tehnique (4-7), and the other uses the Neuron MOS (νmos) transistor priniple (8-). In (5-7) the ganged tehnique proposed in Ref. 4 was employed to build TGs with positive and integer weight and threshold values. Figure 6a shows the iruit struture for these ganged-based TGs. Eah input x i drives a ratioed CMOS inverter; all inverter outputs are hard-wired produing a nonlinear voltage divider whih drives a restoring inverter or hain of in-

9 9 verters whose purpose is to quantize the nonbinary signal at the ganged node (v f ). The design proess for these gates involves sizing only two different inverters. Assuming the same length for all transistors, the transistor widths [W p,w n ] i,b of eah inverter are hosen taking into aount the w i and T values to be implemented. Weight values other than an be realized by simply onneting in parallel the number of basi inverters (inverter with w i =) indiated by the weight value; on the other hand, the value of T is determined by the value of the output inverter threshold voltage. Due to the sensitivity of this voltage and v f to proess variations, the ganged-based TG has a limited fan-in. A good study of this limitation an be found in (2). However, the main drawbak of this TG is the relative high power onsumption. Other interesting stati TGs are based on the νmos transistor. This transistor has a buried floating polysilion gate and a number of input polysilion gates that ouple apaitively to the floating gate. The voltage of the floating gate beomes a weighted sum of the voltages in the input gates, and hene, it is this sum whih ontrols the urrent in the transistor hannel. The most simple νmos-based threshold gate is the omplementary inverter using both p- and n-type νmos devies. A shemati of this TG is shown in Fig. 6b. There is a floating gate, whih is ommon to both the PMOS and NMOS transistors, and a number of input gates orresponding to the threshold gate inputs, x,,,, plus some extra inputs (indiated by V C in the figure) for threshold adjustment. Weights for every input are proportional to the ratio between the orresponding input apaitane, C i, between the floating gate and eah of the input gates, and the total apaitane, inluding the transistor hannel apaitane between the floating gate and the substrate, C han,. Without using the extra ontrol inputs, the voltage in the floating gate is given n by V F = C i V xi Ctot, where C tot = C Chan + C i. As V F beomes higher than the i = n i =

10 0 inverter threshold voltage, the output swithes to logi 0. It is obvious that this νmos threshold gate is simpler than the ganged threshold gate, however its sensitivity to parasiti harges in the floating gate and to proess variations ould limit its effetive fan-in unless adequate ontrol is provided. In partiular, ultraviolet light (UV) erasure is reommended for initialization. b) Dynami threshold-logi gates Two different priniples have been exploited in dynami TG implementations: the biestable operation of simple CMOS lathes, and the apaitive synapse used in artifiial neuron arhitetures. In both ases, ompat gates with low power onsumption, high speed, and high fan-in have been developed (3-5). The first lath-type threshold gate was proposed in (3) and its shemati is shown in Figure 7a. Its main part onsists in a CMOS urrent-ontrolled lath (transistors M 2 /M 5 and M 7 /M 0 ) providing the gate s output and its omplement, and two input arrays ( M 4 M 4n and M 9 M 9n ) onstituted by an equal number of parallel transistors whose gates are inputs of the TG and its sizes are determinate by the orresponding weight and threshold values. Transistor pairs M /M 3 and M 6 /M 8 speify the preharge or evaluation situation, and the two extra transistors M 4n + M 9n + ensure orret operation when the weighted sum of inputs is equal to the threshold value. Preharging ours when reset signal Φ R is at logi 0. Transistors M and M 6 are on, transistors M 3 and M 8 off, and both OUT and OUT are at logi. Evaluation begins when Φ R is at a logi ; transistors M and M 6 are turned off, M 3 and M 8 are turned on, and nodes OUT and OUT begin to be disharged. In this situation, depending on the logi values at the inputs of the two transistor arrays, one of the paths will sink more urrent than the other, making faster

11 the falling of its orresponding output node voltage ( OUT or OUT). When the output node of the path with the highest urrent value is below the threshold voltage of transistors M 5 or M 0, one of them is turned off, fixing the lath situation ompletely. Supply urrent only flows during transitions and, onsequently this TG does not onsume stati power. Input terminal onnetions and input transistor sizes in this TG must be established aording to the threshold value T to be implemented, and to the fat that when all transistors M 4i and M 9i, ( i = 2,,, n ) have the same dimension and the same voltage at their gate terminal, then I in > I ref due to M 4n +. If a programmable TG is required, the best design hoie is to use one of the input arrays for the TG inputs and the other array for ontrol inputs whih must be put to logi or 0 depending on the value of T. For illustration, the operation of a programmable 20-input threshold gate [,,..., ; T] with different values of T is shown in Fig. 8. The iruit in Figure 7b is an alternative realization proposed in (4) for dynami lath-type threshold gates. In this gate, the input transistor arrays ( M xi M yi, i = 0,,, n) are onneted diretly to lath s output nodes and preharging ours when Φ and Φ 2 are at logi 0, putting nodes D, OUT and OUT at logi. For the evaluation phase both Φ and Φ 2 are at logi but Φ 2 must return to the low level before Φ in order to allow the lath swithing. The performane of this TG is similar to that in (3) but it needs more transistors and two different ontrol signals whih have to be obtained from a general lok. The priniple of apaitive synapse has been exploited in the apaitive threshold-logi gate proposed in (5). Its oneptual iruit shemati is shown in Fig. 7 for an n-input gate. It on-

12 2 sists in a row of apaitors C i, i = 2,,, n, with apaitanes proportional to the orresponding input weight, C i = w i C u, and a hain of inverters whih funtions as a omparator to generate the output. This TG operates with two nonoverlapping lok phases Φ R and Φ E. During the reset phase, Φ R is high and the row voltage V R is reset to the first inverter threshold voltage while the apaitor bottom plates are preharged to a referene voltage V ref. Evaluation begins when Φ E is at a logi, setting gate inputs to the apaitor bottom plates. As a result, the hange of voltage in the apaitor top plates is given by n V R = C i ( V i V ref ) Ctot i = where C tot is the row total apaitane inluding parasitis. Choosing adequate definitions for V ref and C i as funtions of the input weight and threshold values, the above relationship an be expressed as n i = V R = ( w i x i T )C u V DD Ctot, that together with the omparison fun- tion of the hain of inverters give the TG operation: V o = V DD if w i x i T, and V o = 0 n if w i x i < T. i = n i = Experimental results from different apaitive threshold-logi gates fabriated in a standard- CMOS tehnology (5) have shown the proper funtionality of this type of threshold gates and its large fan-in apability. Threshold Gate Networks There are funtions whih an not be implemented by a single threshold element. However as TGs realize more omplex funtions than the onventional gates, this setion studies the apa-

13 3 bilities of interonneting TGs so that the potential advantages of realizing digital systems using TGs as building bloks are pointed out. First, the question of whether any boolean funtion an be realized interonneting TGs is addressed. Then the omputation power of suh network is analyzed. Figure 9 shows the model for a feed-forward network of funtional elements. It is the most general type of network without feedbak beause inputs an be onneted to any of the funtional bloks in the network, and the only restrition affeting the funtional bloks to whih the output of one of them an be onneted is that loops are not allowed. The depth of a network is the maximum number of funtional elements in a path from any input to any output. The size is defined as the total number of funtional elements it ontains. In the following a feed-forward network in whih the funtional elements are onventional digital gates (AND, OR, NOT) will be referened as a logi iruit or logi network. It is well known that any boolean funtion an be implemented by a logi iruit, and so, any boolean funtion an also be implemented by a feedforward network of TGs as AND, OR and NOT gates are TGs. However, from a pratial point of view, the above results are not enough. The existene of a determinate network implementing a given funtion an be irrelevant. This is the ase when suh network would ompute the funtion too slow to fulfil speed speifiations, or its ost would be too large. That is, the depth and the size of the network are ritial beause these parameters are related to the speed and to the required amount of hardware respetively. For example, it is well known that any funtion an be implemented with a depth-2 logi network of AND and OR gates (depth-3 network of NOT- AND-OR gates if input variables are in single rail). However, it is also well known that there are ommon funtions for whih the number of required gates in suh implementations grows up exponentially with the number of variables, and so they are not realized in two levels. From a different point of view, there are funtions whih an not be implemented by a polynomial

14 4 sized network with onstant-depth (independent of the number of variables) resulting in too large omputation time for large n. It follows from the previous arguments that a more realisti problem is determining the existene of a onstant-depth network with size polynomial in n, O(n), for a boolean funtion of n variables. There are a number of funtions for whih the answer to the above question is negative for logi networks and affirmative for threshold networks. Consider for example the parity funtion, f parity ( x,,, ), whih is if and only if an even number of its inputs are logial. No logi iruit with polynomial (in n) number of unbounded fan-in AND-OR-NOT gates an ompute it in onstant-depth (6). In Figure 0a a depth-2 logi network implementing parity for n = 4 is depited. For an arbitrary n, its size is 2 n +. A depth-2 threshold network for f parity of four variables is shown in Figure 0b. For an arbitrary n only (n+) gates are required. The parity funtion belongs to the more general lass of symmetri funtions whih an be effiiently implemented by threshold networks and whih have reeived muh attention. Symmetri funtions are the subjet of the next subsetion Threshold Networks for Symmetri Funtions Symmetri funtions are not partiularly easy to realize using traditional logi gates. However, an important feature of threshold logi gates is their apability for obtaining implementations of symmetri funtions by simple networks.

15 5 Classially, two main solutions have been onsidered depending on the availability of the input variables of the network. Muroga () proposed a solution when the input variables are available only at the first-level gates and the network has feed-next interonnetions, then any symmetri funtion of n variables an be implemented by a network whih has at most (n+) threshold gates in two levels. To show that, let us suppose that the symmetri funtion is if and only if the number of s in the n variables, given by k, is in one of the ranges k k k, k 2 k k 2,..., k s k k s. Figure shows the threshold gate network to implement this funtion. If the number of s in the input variables, k, is k i k k i, i s, all the TGs whose thresholds are equal to or smaller than k have outputs of, and the other TGs have outputs of 0. Then, there are (2i-) gates with output. Among them, i gates are onneted to the output gate with weight +, and (i-) gates with weight. Thus the weighted sum of these inputs is +, and the output gate will give an output of. When k i + k k i +, there are 2i gates with output, but the weighted sum of these inputs to the seond TG is 0 and, onsequently, the output of that output gate is 0. Minnik () authored a solution when the input variables are available at gates of any level. A symmetri funtion of n variables an be implemented by a network whih has at most + n -- TGs in at most two levels. Here x 2 denotes the integral part of x. To show that, let us suppose that the symmetri funtion is if and only if the number of s in the n variables, given by k, is in one of the ranges k k k, k 2 k k 2,..., k s k k s. Figure 2 shows the threshold gate network to implement the symmetri funtion. If the number of s in the input variables, k, is k i k k i, i s, all the TGs with threshold equal to or smaller than k have output of. As k i + < k i k k i, then there are (i-) TGs giving an output of,

16 6 whih add i w j j = = ( k i k ) to the weighted sum of the output threshold gate. The weighted sum of that gate will be: ( k i k ) + k whih, when ompared to k, results in a number that is equal to or greater than zero and, in onsequene, the output of the output threshold gate is. The ase for an output of 0 an be shown in a similar manner. Also, it an be found an equivalent realization by expressing the outputs of the first-level threshold gates as inverted instead of weighted negatively. An interesting solution for the modulo-2 sum (parity) of n variables was proposed by Kautz (). It is realizable with at most s = ( + log 2 n ) threshold gates. The feed-forward network proposed is shown in Figure 3a and the synthesis problem an be easily extended to solve a general symmetri funtion. Let us onsider the general feed-forward solution shown in Figure 3a when partiularized to s=5. Figure 3b shows the output values of the gates of this network in terms of the number of s in the input variables. It an be easily seen that the number of s in the input variables at whih transitions from the value 0 to our in g k, defines the oppositely diret transitions from to 0 in g k g k 2,,, g 0. Also, it is important to onsider that although T 3, T 2, T 2 w 32, T, T w 2, T w 3, T 0, T 0 w 0, T 0 w 20, T 0 w 30 for g 3, g 2, g and g 0 are independent and arbitrarily determined, some of the relations for g and g 0 ( T w 3 w 2, T 0 w 20 w 0, T 0 w 30 w 0, T 0 w 30 w 20, and T 0 w 30 w 20 w 0 ) are onsequently determinated. Thus, the synthesis of a general symmetri funtion an beome very omplex beause of this mutual dependene of parameters. Solutions proposed by Muroga and Minnik implement symmetri funtions in an O(n) depth- 2 threshold network. Reduing the size of the network signifiantly from O(n) requires an in-

17 7 reasing of the network depth beyond 2. Reently it has been shown (7) that any symmetri funtion of n variables an be implemented with a depth-3 threshold network with at most 2 n+ O( ) threshold gates, i.e., an inreasing of in the depth allows an implementation with a gate ount redued by a fator of O( n). Threshold Networks for Arithmeti Funtions Usually when implementing arithmeti-like funtions by threshold networks, the required weights an grow exponentially fast with the number of variables. It is undesirable beause the requirements of high auray it plaes on the atual implementations. An example is the omparison funtion f omp ( x,,,, y, y 2,, y n ) whih takes as input two n-bit binary numbers x = -...x, and y =y n y n-...y, and produes output equal to if and only if x y. Figure 4a shows a TG implementing the funtion. The depth-2 network in Figure 4b would be preferable for moderately large value of n beause the smaller weights it requires. A sub-lass of the threshold gates, those for whih the weights are polynomially bounded by the number of input variables is more pratial. Restriting the allowed weights does not limit too muh the omputational power of the network. It has been shown (8-9) that any depth-d polynomialsize threshold iruit an be implemented by a depth-(d+) polynomial-size network of the restrited threshold elements. Interesting result have been derived for funtions suh as multiple addition, multipliation, division or sorting whih have been shown to be omputable by small onstant-depth polynomialsize threshold networks. Different proposed implementations exhibit different depth-size tradeoff. Some results onerning optimal depth threshold networks are given in (20). It is demonstrated that multipliation, division and powering an be omputed by depth-3 polynomial-size threshold iruits with polynomially bounded weights.

18 8 The effiient threshold networks derived for these funtions rely in many ases on the underlying new omputation algorithms. One example is the blok save addition (BSA) priniple for multiple addition. Siu showed (2) that the sum of n numbers an be redued to the sum of two numbers by using the BSA priniple. The key point of this tehnique is the separation of the n numbers in olumns of logn -bits whih are separately added. Eah sum is at most 2 logn -bits long and hene it overlaps only with the sum of the next olumn. So a number is obtained by onatenating the partial sums from the olumns plaed in even positions and another number with the onatenation of the sum from the odd olumns. In general, the realizations introdued so far an not be diretly applied if the fan-in of the TGs is onstrained to be not more than m, m<<n, where n stands for the number of input variables. Thus, another area whih is reeiving attention is that of deriving depth-size trade-off for threshold networks implementing arithmeti-like funtions with a simultaneous bound on the maximum allowable fan in. Let us resort again to the parity funtion in order to illustrate the above statement. In (22) it is shown that the parity funtion of n inputs an be omputed using a threshold iruit of size Onm ( 2d ) ( ), depth Odn ( log logm) and fan-in bounded by m for every integer d > 0. Threshold Network Synthesis The signifiane of the above results is that assuming TGs an be built with a ost and delay omparable to that of logi gates, many basi funtions an be omputed muh faster and/or muh heaper using TGs than using logi gates. This is one of the motivation for investigating devies able to implement TGs. However, the usefulness of threshold logi as a design alternative, in general, is determined not only by the availability, ost and apabilities of the basi building bloks, but also by the existene of synthesis proedures. The problem to be solved at

19 9 this level an be stated as: given a ombinational logi funtion, desribed in the funtional domain (by means of truth tables, logi expressions et.), derive a network of the available building bloks realizing f and whih is optimal aording to some design riteria. Many logi synthesis algorithms exist targeting onventional logi gates but few have been developed for TGs, although the problem was addressed as early as the beginning of the 70 s by Muroga. The proedure desribed by this author () transforms the problem of deriving the smallest (lowest gate ount) feed-forward network realizing a given funtion in a sequene of mixed integer linear programming (MILP) problems. The problem of determining whether a given funtion f an be realized by a feed-forward threshold network with M gates, and if it an, determining the weights and the threshold for eah of the M elements an be formulated as a MILP problem (the ost funtion is usually the total weight sum of the network). Starting with M equal to one and inrementing M until a feasible MILP problem is enountered, the implementation with less gates is derived. Clearly exat approahes are pratial only for small instanes of the synthesis problem. Main limitation seems to be the number of variables that the funtion being synthesized depends on, beause the number of inequalities and variables in the MILP problem to be solved grow up exponentially with n. Thus, heuristi approahes are more relevant. Conerning two-level (depth-2) threshold networks, an algorithm, LSAT (23), inspired in tehniques used in lassial two-level minimization of logi iruits has been developed. The ore of the algorithm performs as follows. Given a two-level threshold network satisfying ) weights of first level TGs are restrited to the range [-z, +z]; 2) weights of the seond level gate are all equal to one and its threshold is S, another threshold network whih also satisfies previous onditions and 2, with a minimal number of gates is obtained. This operation is repeated inreas-

20 20 These unsatisfatory results provided by linear filters in signal and image proessing have been overome by resorting to non linear filters. The more known one is perhaps the median filter whih has found a widespread aeptane as the preferred tehnique to solve the signal restoration problem when the noise has an impulsive nature or when the signals have sharp edges whih must be preserved. But the median filter has inherent problems beause its output de- ing S by one until a value of S is reahed for whih no solution is found. As a two-level AND- OR network is a threshold network of the type handled by the proedure (z=, S=), the algorithm is started with it. Suh a two-level iruit is easy to obtain and in fat is a standard input for other synthesis tools. LSAT has a run time polynomial in the input size given by n z, where n stands for the number of variables and z defines the allowed range for the weights. This means CPU time inreases if large weights are required. The pratial use of synthesis proedures for TGs is not restrited to the design of integrated iruits but to areas suh as artifiial neural networks or mathing learning. Different problems enountered in these fields are naturally formulated as threshold network synthesis problems. Appliation to Median and Stak Filters Sine some time ago, linear filters have been widely used for signal proessing mainly due to their easy design and good performane. However, linear filters are optimal among the lass of all filtering operations only for additive Gaussian noise and so, problems suh as redution of high frequeny and impulsive noise in digital images, smoothing of noisy pith ontours in speeh signal, edge detetion, image preproessing in mahine reognition and other related with the suppression of noise that is non-gaussian, nonadditive, or even not orrelated with the signal an be diffiult to solve (24).

21 2 pends only on the values of the elements within its window. So, a median filter with a window width of n=2l+ an only preserve details lasting more of L+ points. To preserve smaller details in the signal, a smaller window width must be used. But the smaller this window width is, the poorer the filter noise redution apability beomes (25). This ontradition an be solved by inorporating in the filter output the index order of the sequene of elements. It is typially done by weighting filter input values aording to their relative sequene index order. This idea leads in a natural way to the onept of weighted median (WM) filter (26), whih has the same advantages as the median filter but is muh more flexible in preserving desired signal strutures due to the defining set of weights. Median and weighted median filters are well known examples of a larger lass of non linear filters: the stak filters, whih also inlude the max-median filters, the mid-range estimators and several filters more. Stak filters are a lass of sliding finite width window, nonlinear digital filters defined by two properties alled the threshold deomposition (a superposition property) and the staking property (an ordering property) (24). The threshold deomposition of an M-valued signal X = ( X, X 2,, X N ), where X i { 02,,,, M }, i=,, N, is the set of (M-) binary signals x,,..., x M-, alled threshold signals, defined as: j ifx, i j x i =, j=,, M 0, else (3) From the above definition, it is lear that M j x i j = j =, i {,, N }, and also that the x i X i are ordered, i.e., x i 2 M x i x i, i {,, N }. This ordering property is alled the staking property of sequenes.

22 22 Two binary signal u and v, staks if u i, i=,, N. Let us suppose that both signals are v i filtered with a binary window filter of width L, (i.e., we use a boolean funtion B: { 0, } L { 0, } for the filtering operation, whih results in B(u) and B(v)). The binary filter B exhibits the staking property if and only if B( u) B( v) whenever u v. The stak filter S B (X) is defined by a binary filter B(x) as follows: M S B ( X ) = B( x j ) j = (4) The threshold deomposition arhiteture of stak filters means that filtering an M-valued input signal by the stak filter S B is equivalent to threshold deompose the input signal to M- binary threshold signals, filtering eah binary signal separately with the binary filter B, and finally adding the binary output signal together to reonstrut the M-valued signal. As stak filters possess the staking property, this reonstrution setion needs only detet the level just before the transition from to 0 takes plae. Figure 5 illustrates the threshold deomposition arhiteture of a stak filter with a window width of 3 for the 4-valued input signal shown at the upper left orner. The binary signals are obtained by thresholding the input signal at levels, 2 and 3. Binary filtering is independently performed by the digital funtion Bab (,, ) = a + b, in whih ab,, are the bits, in time order appearing in the filter s window. In the original integer domain of the M-valued input signal, the stak filter orresponding to a positive boolean funtion (PBF) an be expressed by replaing logial operators AND and OR with MIN and MAX operations, respetively. In onsequene, the output of a stak filter is a

23 23 omposition of maximum and minimum operations on the samples in the window. For the example in Figure 5, this means that the operation performed by S B is S B ( A, B, C) = MAX { MIN{ A, C}, B}. Both filtering operations are represented in Figure 5: by threshold deomposition if the slender arrows are followed, and diretly, by the stak filter S B, following the heavy arrows. Next question is to know whih binary funtions possess the staking property. It has been shown that the neessary and suffiient ondition for this is that the binary funtion is a PBF, i.e., positive in all its variables. These funtions are a subset of unate funtions whih have the property that eah one possesses a unique minimum sum-of-produts (s-o-p) expression, and hene, eah stak filter an be desribed in terms of a unique minimum s-o-p boolean expression. Finally, as it has been previously shown, threshold funtions are a subset of unate funtions. Stak filters that are based on TGs with nonnegative weights and nonnegative threshold values are alled weighted order statistis (WOS) filters. It an be very larifying to show the relations of the more usual members of the lass of stak filters, namely, weighted order statisti (WOS), weighted median (WM), order statisti (OS), and standard median (SM) filters. In Figure 6 these relations are shown by means of boxes and arrows. Eah box orresponds to a filter sublass speified by the integer domain filter and the binary one. The arrows indiate the ontaining onditions between lasses of filters. From a pratial point of view, there are several options for the VLSI implementation of the PBF of a stak filter: binary logi gates, sort-and-selet iruits or ount-and-ompare iruits. If logi gates or a Programmable Logi Array (PLA) are used, a number of terms bounded by n or n n/2 n/2 for a window width of n an be obtained. The hardware omplexity for

24 24 sort-and-selet iruits is O(nlogn) and O(n) for ount-and-ompare iruits. The PBF an also be realized as a look-up table by a 2 n sized RAM or ROM, and if a RAM is used, programmable PBF-based filters an be made. In the ase of a WOS filter, its PBF an be realized by a TG. It onstitutes a great advantage beause the number of produt terms or sum terms of the PBF an be as large as n, while T the representation of a TG needs only (n+) omponents. Therefore, while the implementation of a generi stak filter an be very diffiult, the implementation of the sublass of WOS filters an be affordable if an effiient realization of TGs is used. Referenes. S. Muroga, Threshold Logi & its Appliations, New York: John Wiley & Sons, Z. Kohavi, Swithing and Finite Automata Theory, New Delhi: Tata MGraw Hill Pub. Co. Ltd., E.J. MCluskey, Logi Design Priniples: with emphasis on testable semiustom iruits, Englewood Cliffs, NJ: Prentie Hall, K.J. Shultz, R.J. Franis, and K.C. Smith: Ganged CMOS: Trading Standby Power for Speed, IEEE J. Solid-State Cir., 25, (3): , C.L. Lee, C-W. Jen, CMOS Threshold gate and networks for order statisti filtering, IEEE Tr. on Cir. and Syst. -I, 4, (6): , J.M. Quintana, M.J. Avedillo and A..Rueda, Hazard-free edge-triggered D flipflop based on Threshold Gates, Elet. Let. 30, (7), , 994.

25 25 7. J.M. Quintana, M.J. Avedillo, A..Rueda and C. Baena, Pratial Low-Cost CMOS realization of Complex Logi Funtions, Pro. of European Conf. on Ciruit Theory and Design, ECCTD 95, pp T. Shibata, T. Ohmi, A funtional MOS transistor featuring gate level weighted sum and threshold operations, IEEE Trans. on Eletron Devies, 39, (6): , T. Shibata, T. Ohmi, Neuron MOS binary-logi integrated iruits- Part I: Design fundamentals and soft-hardware-logi iruit implementations, IEEE Trans. Eletron Devies, 40, (3): , T. Shibata, T. Ohmi, Neuron MOS binary-logi integrated iruits- Part II: Simplifying Tehniques of Ciruit Configuration and their Pratial Appliations, IEEE Trans. Eletron Devies, 40, (5): , W. Weber, et al., On the appliation of the Neuron MOS Transistor Priniple for Modern VLSI Design, IEEE Trans. Eletron Devies, 43, (0): , N. Balabbes, A. J. Guterman, Y. Savaria, M. Dagenais, Ratioed Voter Ciruit for Testing and Fault-Tolerane in VLSI Proessing Arrays, Tran. Ciruits and Systems- I, 43, (2): 43-52, M. J. Avedillo, J. M. Quintana, A. Rueda and E. Jiménez, Low-power CMOS thresholdlogi gates, Eletronis Letters 3, (25): , J. Fernández Ramos, J.A. Hidalgo López, M. J. Martín, J.C. Tejero, A. Gago, A threshold logi gate based on loked oupled inverters. Int. J. Eletronis, 84. (4): , H. Özdemir, A. Kepkep, B. Pamir, Y. Leblebii, U. Çilingiroglu, A Capaitive Threshold- Logi Gate, IEEE J. Solid-State Cir, 3, (8): 4-50, M.Furst, J. B. Saxe and M. Sipser, Parity, iruits and the polynomial-time hierarhy, Pro. IEEE Symp. Found. Comp. Si., pp , K-Y. Siu, V.P. Royhowdhury and T. Kailath, Depth-Size Tradeoffs for Neural Computation, IEEE Trans. on Computers, 40, (2): , 99.

26 26 8. M. Goldmann, J. Hastad and A. Razborov, Majority Gates vs. General Weighted Threshold Gates, in Pro. 7th Annual Conferene on Struture on Complexity Theory, pp M. Goldmann and M. Karpinski, Simulating Threshold Ciruits by Majority Ciruits, In Pro. of the 25th annual ACM Symposium on the Theory of Computing, pp , K. Siu and V.P. Royhowdhury, An Optimal-depth Threshold Ciruit for Multipliation and Related Problems, SIAM Journal of Disrete Mathematis, 7, (2): , K. Siu and J. Bruk, Neural Computation of Arithmeti Funtions, Pro. IEEE, 78, (0): , K. Siu, V.P. Royhowdhury and T. Kailath, Toward Massively Parallel Design of Multipliers, Journal of Parallel and Distributed Computing, 24: 86-93, A. L. Oliveira and A. Sangiovanni-Vinentelli, LSAT- An Algorithm for the Symthesis of Two Level Threshold Gate Networks, Pro Int. Conf. on Computer Aided Design, pp , P.D. Wendt, E.J. Coyle and N.C. Gallagher Jr., Stak Filters, IEEE Trans. on Aoustis, Speeh, and Signal Proessing, 34, (4), 898-9, B.I. Justusson, Median Filtering: Statistial Properties. In T.S. Huang (ed.), Two-Dimensional Digital Signal Proessing II. New York: Springer-Verlag, L. Yin, R. Yang, M. Gabbouj, and Y. Neuvo, Weighted Median Filters: A Tutorial, IEEE Trans. on Ciruits and Systems-II: Analog and Digital Signal Proessing, 43, (3), 57-92, 996.

27 27 Figures: Figure. Separation of points of f by a hyperplane. x x 3 f(x,,x 3 ) hyperplane x 3 2x + + x 3 = 3, true point of f,, false point of f x Figure 2: Threshold gate symbols: (a) all weights equal to ; (b) weights not equal to. x T x w x 2 f w 2 f w n T (a) (b) Figure 3: Elementary properties of threshold funtions. f ( x) [w; T] x f () f ( x) [-w; -T] f ( x) [-w; T- w i ] f [w; -T+ w i ] f ( x) f d ( x)

28 28 Figure 4: Examples of a straightforward proedure for threshold funtion identifiation. x x 3 h(x,,x 3 ) T w 3 < T w 2 < T w 2 + w 3 T w < T w + w 3 T w + w 2 T w + w 2 + w 3 < T no solution h is not a threshold funtion x x 3 f(x,,x 3 ) T w 3 < T w 2 T w 2 + w 3 < T w T w + w 3 T w + w 2 T w + w 2 + w 3 T w = 2, w 2 =, w 3 = 3, T = 0 f is a threshold funtion represented by the vetor: [2,, -2; 0]

29 29 Figure 5: Examples of seond proedure for threshold funtion identifiation x x 3 h(x,, x 3 ) Unateness heking not passed x 3 h x (, x 3 ) x 3 h x (, x 3 ) As neither h xi h xi nor h xi h xi are verified, then h is not a threshold funtion x x 3 f ( x,, x 3 ) Unateness heking: f positive in x and f negative in x Funtion g positive in all variables x x 3 f ( x,, x 3 ) = g( x,, x 3 ) A A 0 0 A A 3 0 A A 5 0 A 6 0 A minimal true assignments {A, A 4 } maximal false assignments {A 2 } 4.- Redued set of inequalities: w 3 w 2 w T < T, T solution for g( x,, x 3 ): [2,, 2; 2] 5.-Solution for f ( x,, x 3 ): [2,, -2; 0]

30 30 Figure 6: Stati threshold logi gates: (a) ganged threshold gate, (b) νmos threshold gate. [W p /L p, W n /L n ] i x [W p /L p, W n /L n ] b V x F PMOS v f f x 3 f CMOS inverters V C NMOS (a) (b)

31 3 Figure 7: Dynami threshold gates: (a) lath type threshold gate, (b) alternative lath type threshold gate, () apaitive type threshold gate. V DD V OUT Φ R M M 2 M 7 M 6 Φ R V OUT OUT OUT Φ R M 3 M 8 Φ R W/2L M 4n+ I in I ref V xn V x2 V x V y V y2 V yn W/L W/L W/L W/L W/L W/L M 4n M 42 M 4 M 9 M 92 M 9n W/2L M 9n+ M 5 M 0 (a) V DD Φ Φ M M 2 OUT OUT M 3 M 4 Φ Φ Φ 2 Φ Φ2 V x V x2 V xn V yn V yn- V y M x0 M x M x2 M xn M yn M yn- M y M y0 (b) Φ R V R V o C C j C n Φ R Φ E V ref V V j V n Φ R Φ E ()

32 32 Figure 8: Simulation results for a progammable threshold gate implemented by the iruit of Figure 7a. Φ R V OUT or-gate (T=) V OUT maj-gate (T=0) V OUT and-gate (T=20) Figure 9: Feed-forward network of funtional elements. x FU. x. FU 2 x. FU 3 onnetion an exist.... x. FU M- x.. FU M

33 33 Figure 0: Networks realizing f parity for n = 4. a) logi network, b) threshold network. x x 3 x 4 x x 3 x 4 x x 3 x 4 x x 3 x 4 x x 3 x 4 x x 3 x 4 x x 3 x 4 x x 3 x 4 & & & & & & & & + f parity x 2 x 3 x 4 x 2 x 3 x 4 x 2 x 3 x 4 x 2 x 3 x f parity (a) (b) Figure : Muroga solution to the threshold gate network implementation of a symmetri funtion. x k x k s x k + x k s f(x,..., )

34 34 Figure 2: Minnik solution to the threshold gate network implementation of a symmetri funtion. x k + x k 2 + x k s + x w w 2 w s k f(x,..., ) w j = k j + k j, ( j = 2,,, s ) n + k s, if k s < n w s = 0, if k s = n

35 35 Figure 3: Kautz solution to the threshold gate network implementation of a symmetri funtion. (a) general struture, (b) transitions of output values for s=4. x g s- T s- x w s- s-2 g s-2 T s-2 x w s- s-3 w s-2 s-3 g s-3 T s-3 w s- 0 w s-2 0 w s-3 0 (a) x w 0 T 0 g 0 g 3 g 2 g g 0 T 0 -w 30 -w 20 -w 0 T -w 3 -w 2 T 0 -w 30 -w 20 T 2 -w 32 T 0 -w 30 -w 0 T -w 3 T 0 -w 30 T 3 T 0 -w 20 -w 0 T -w 2 T 0 -w 20 T 2 T 0 -w 0 T T 0 (b)

36 36 Figure 4: Networks realizing f omparison a) depth- network. b) depth-2 network. x 2. 2 n- y - y 2-2. y n -2 n- 0 f omparison x 2 2 x r. 2 r- y y - 2 y r. x 2 2 x r. 2 r r- y - y 2-2 y r. -2 r- 0 x r + r+2 2 r. 2 y r- r+ - y r+2-2 y 2r. -2 r- x r + r+2 2 r. 2 r- y r+ - y r+2-2 y 2r. -2 r t- 2 t- 2 t - f omparison (a) -r + n-r r- y n-r + y - n-r +2 y n r- r t = = log 2 n n r -r + n-r r- y n-r + y - n-r +2 y n r- 0 (b)

37 37 Figure 5: Illustration of threshold deomposition and the staking property. Input signal Integer signals: X i Threshold at, 2, and 3 (threshold deomposition) Binary signals: 3 x i S B filtering B Output signal Add binary outputs (staking property) x i B 00 x i 0 B Figure 6: Relations of linearly separable sublasses of stak filters. Positive Boolean Funtions Stak filters, MAX-MIN network Threshold gates, Linearly separable PBF Weighted Order Statisti filters (WOS) Linearly separable selfdual PBF Weighted Median filters (WM) Linearly separable isobari PBF Order Statisti filters (OS) Selfdual linearly separable isobari PBF Standard Median filter (OS)