Fault Tolerant Variable Block Carry Skip Logic (VBCSL) using Parity Preserving Reversible Gates

Transcription

1 Fault Tolerant Variable lok Carry Skip Logi (VCSL) using Parity Preserving Reversible Gates Md. Saiful Islam, M. M. Rahman*, Zerina egum, and M. Z. Hafiz Institute of Information Tehnology, University of Dhaka, Dhaka-1000, angladesh *Dept. of Computer Siene and Engineering, Amerian International University-angladesh, Dhaka-113, angladesh Abstrat Reversible logi design has beome one of the promising researh diretions in low power dissipating iruit design in the past few years and has found its appliation in low power CMOS design, digital signal proessing and nanotehnology. This paper presents the effiient design approahes of fault tolerant arry skip adders (FTCSAs) and ompares those designs with the existing ones. Variable blok arry skip logi (VCSL) using the fault tolerant full adders (FTFAs) has also been developed. The designs are minimized in terms of hardware omplexity, gate ount, onstant inputs and garbage puts. esides of it, tehnology independent evaluation of the proposed designs learly demonstrates its superiority with the existing ounterparts. Index Terms Reversible Logi, Parity Preserving Reversible Gate, FTFA, Carry Skip Adder, VCSL. I. ITRODUCTIO Irreversible logi iruits dissipate heat in the amount of kt ln Joule for every bit of information that is lost irrespetive of their implementation tehnologies, where k is the oltzmann onstant and T is the operating temperature [1]. Information is lost when the iruit implements nonbijetive funtions. Therefore, in irreversible logi iruit the input vetor annot be reovered from its put vetors. Reversible logi iruit by definition realizes only those funtions having one-to-one mapping between its input and put assignments. Hene in reversible iruits no information is lost. Aording to [] zero energy dissipation would be possible only if the network onsists of reversible gates. Thus reversibility will beome an essential property in future iruit design. Reversible logi imposes many design onstraints that need to be either ensured or optimized for implementing any partiular oolean funtions. Firstly, in reversible logi iruit the number of inputs must be equal to the number of puts. Seondly, for eah input pattern there must be a unique put pattern. Thirdly, eah put will be used only one, that is, no fan is allowed. Finally, the resulting iruit must be ayli [3-5]. Any reversible logi design should minimize the followings [6]: Garbage Outputs (GO): puts that are not used as primary puts are termed as garbage puts Constant Inputs (CI): onstants are the input lines that are either set to zero(0) or one (1) in the iruit s input side Gate Count (GC): number of gates used to realize the system Hardware Complexity (HC): refers to the number of basi gates (OT, AD and EXOR gate) used to synthesize the given funtion In addition of the above four, the following two measures an be taken into onsideration in designing a digital system: Area Consumption (AC): the area onsumed by a design an be alulated as the sum of the width of individual gates used to realize the system. AC = n w i i= 1 Path Delay (PD): total number of gates on the way of final put. Parity heking is one of the widely used mehanisms for deteting single level fault in ommuniation and many other systems. It is believed that if the parity of the input data is maintained through the omputation, no

2 intermediate heking would be required [7-8]. Therefore, parity preserving reversible iruits will be the future design trends towards the development of fault tolerant reversible systems in nanotehnology. A gating network will be parity preserving if its individual gates are parity preserving [7]. Thus, we need parity preserving reversible logi gates to onstrut parity preserving reversible iruits. This paper presents effiient approahes for designing fault tolerant arry skip adder using modified IG gate (MIG) and its basi building blok FTFA proposed in [9-10] [17]. The proposed arry skip adder is optimized in terms of gate ount, garbage puts and onstant inputs and offers less hardware omplexity. Variable blok arry skip logi using FTFA iruits has also been given. Finally, tehnology independent evaluation of the proposed arry skip adders has been presented. II. REVERSILE LOGIC GATES A gate that implements any bijetive funtion involving n inputs and n puts is alled an n* n reversible logi gate. There exist many reversible gates in the literature. Among them * Feynman gate [11] (shown in Fig. 1), 3*3 Fredkin gate [1] (shown in Fig. ), 3*3 Toffoli gate [13] (shown in Fig. 3) and 3*3 Peres gate [1] (shown in Fig. ) are the most referred. Feynman (FG), Fredkin (FRG) and Peres (PG) gates are one through gates, that is, one of its put lines is idential to one of its input lines. On the other hand, Toffoli gate is two through, that is, two of its puts are idential to two of its inputs. It an be easily verified that all of these gates are reversible. Eah gate has an equal number of input and put lines. For eah input ombination there is a unique put ombination. Fig. 1(a) * Feynman gate A P Q Fig. 1(b) Truth table of Feynman gate Fig. (a) 3*3 Fredkin gate A C P Q R Fig. (b) Truth table of Fredkin gate Fig. 3(a) 3*3 Toffoli gate

3 A C P Q R Fig. 3(b) Truth table of Toffoli gate Fig. (a) 3*3 Peres gate A C P Q R Fig. (b) Truth table of Peres gate III. PARITY PRESERVIG REVERSILE GATES A reversible gate will be parity preserving if the parity of the inputs mathes the parity of the puts. Mathematially, a reversible gate having n input lines and n put lines will be parity preserving if and only if: I I I O O L 1 L n 1 O n where I i and O j are the input and put lines. ot all of the gates presented in setion II are parity preserving. Only Fredkin gate (FRG) is parity preserving and it an be easily verified by examining its truth table. That is, Fredkin gate maintains. It an also be said that the Fredkin gate is zero preserving A C P Q R (one preserving as well) and therefore onservative [15]. Other parity preserving reversible logi gates are 3*3 Feynman Double gate [7] (shown in Fig. 5), 3*3 ew Fault Tolerant gate [16] (shown in Fig. 6) and newly proposed * IG gate [9-10] (shown in Fig. 7). Feynman Double gate an be as used as the fault tolerant opying gate when it s and C input lines are set to onstants. The first three put lines of IG gate produe the same put as PG gate. The fourth one an be onsidered as garbage if we wish to replae PG by IG. The fourth put line of IG gate an also be minimized to redue the hardware omplexity in [17] as follows: D ( A D) A D The modified version of IG (that is, MIG gate) is depited in Fig. 8. Fig. 5 3*3 Feynman Double gate

4 Fig. 6 3*3 ew Fault Tolerant gate Fig. 7 * IG gate Fig. 8 * MIG gate IV. SYTHESIS OF FAULT TOLERAT REVERSILE CARRY SKIP ADDER The basi building blok of many omplex omputational systems is the full adder (FA). Realization of the effiient reversible full adder iruit given in [3-5] inludes two 3*3 Peres gates (shown in Fig. 9). The iruit is minimized in terms of gate ount, garbage puts, onstant inputs and hardware omplexity. It has also been proved in [3-5] that a reversible full adder iruit an be realized with at least two garbage puts and one onstant input. Fig. 9 Reversible full adder iruit given in [3-5] Fault tolerant logi synthesis of reversible full adder iruit requires that its individual gate unit must be fault tolerant reversible gates. It has been proved in [9-10] that a fault tolerant reversible full adder iruit requires at least three garbage puts and two onstant inputs. This paper will use MIG gate for fault tolerant reversible full adder implementation as used in [17] and will thereby minimize the hardware omplexity of the presented systems. The Fig. 10 shows a 1-bit fault tolerant reversible full adder realized using two MIG gates. Fig. 10 Fault tolerant reversible full adder iruit inludes two * MIG gates The blok diagram of the fault tolerant reversible full adder an be depited as follows: Fig. 11 lok diagram of fault tolerant full adder

5 The most straightforward realization of a final stage adder for two -bit operands is ripple arry adder (RCA). The RCA requires full adders (FAs). The arry of the i th FA is onneted to the arry in of the (i+1) th FA. The Fig. 1 shows a reversible logi implementation of an -bit final stage fault tolerant ripple arry adder. A arry-skip adder redues the arry-propagation time by skipping over groups of onseutive adder stages. The arry-skip adder is usually omparable in speed to the arry look-ahead tehnique, but it requires less hip area and onsumes less power [15]. The Fig. 13 shows a reversible logi implementation of a -bit fault tolerant arry skip adder blok proposed in [17]. The blok arry input in is propagated as the blok arry put, if the blok propagate P is one. The arry skip adder worst ase delay is the when the arry generated in the very first full adder ripples through all full adder stages in the first blok, generates for the first blok, skips all the intermediate bloks, and ripples through the full adder stages of the last blok. This paper presents two new fault tolerant reversible arry skip adders, shown in Fig. 1 and Fig. 15. The arry skip logi in Fig. 1 has been developed using 3 FTs and 1 FRG instead of FTs and 1 FG as in [17]. The arry skip logi in Fig. 15 uses FRGs as in [15] and 1 FG to avoid the fan. A bit FTFA requires MIG using the iruit in Fig. 10. The input AD gate requires -1 FTs in Fig. 1. Therefore, a bit arry skip adder blok requires MIG, -1 FTs, 1 FRG and 1 FG using the FTFA iruit in Fig. 10. d ripple ( ) = + 3 (1) Consider the -bit arry skip adder in Fig. 1 generating a blok arry via arry ripple through the FTFAs. The least signifiant FTFA will require a path delay of MIGs to generate 1 from the addends. Then the arry ripples through the subsequent FTFAs with a path delay of 1 MIG per bit. Finally, is generated by the FRG in the left of Fig. 1. Therefore, the delay to generate blok arry (via ripple) with a bit arry skip adder blok is: d skip = () The total (worst ase) delay T fixed ( ) log + of an bit arry skip adder with fixed blok size is the sum of the ripple arry delay through the first arry skip adder blok, the arry skip delays through the intermediate bloks and the ripple arry delay through the last blok, or However, the assumption designs. Thus, (3) an be rewritten as T ( + 3) + ( log + ) + ( + 3) = log fixed (3) is valid for the small blok sizes appliable to arry skip adder Fig. 1 Reversible logi implementation of fault tolerant n-bit ripple arry adder [17]

6 Fig. 13 Reversible logi implementation of fault tolerant -bit arry skip adder [17] Fig. 1 Proposed fault tolerant reversible -bit arry skip adder, CSL using FTs Minimizing Tfixed Substituting (5) into () gives The alulation of Fig. 15 Proposed fault tolerant reversible -bit arry skip adder, CSL using FRGs with respet to blok size gives Tfixed = + + T fixed () 1 = 0 or opt = (5) = + T fixed (6) for the arry skip adder shown in Fig. 15 is same. The only differene between these

7 two designs is in the CSL implementations. The CSA in Fig. 15 uses FRGs instead of FTs to implement -input AD gate. I. VARIALE LOCK CARRY SKIP ADDER Varying the size of the arry skip bloks an redue the total worst ase delay, sine arries generated or absorbed in the adder enter have shorter data paths [15]. With loss of generality, the first and last arry skip bloks are b bits wide, and the arry skip adder is divided into t bloks, where t is even. Let s assume that arry skip blok sizes are: t t b b + 1 L b + 1 b + 1 L b + 1 b (7) Summing the number of bits in the bloks, equating to, and rearranging gives T var iable = t 1 t + b (8) The total (worst ase) delay of an bit arry skip adder with the variable blok size is the sums of the ripple arry delay through the first arry skip adder blok, the arry skip delays through the intermediate bloks and the ripple arry delay through the last blok. Assuming the variable blok sizes in (7), the total delay is: k Again assuming log Using the identity To simplify (10) yields k t b+ 1 k ( b + 3) + ( log + ) T (9) var iable = k = b+ 1 and rearranging gives t b+ 1 T = b + t + k (10) var iable Y k = X Inserting (8) into (11) and olleting terms gives The optimal number of bloks is found with Y K = k = b+ 1 ( Y + 1) X ( X 1) t t b + 1 b + ( b)( b + 1) Tvar iable = b + t + (11) t 15t bt = b 8 15t 3 Tvar iable + + t = (1) T t = 15 t = 0 or t opt = (13) 15 Therefore, the optimal blok size arry skip adder has delay var 3 = + 15 T iable (1)

8 II. RESULT AD DISCUSSIO The presented arry skip adder iruits an be evaluated in terms of hardware omplexity, gate ount, onstant inputs and garbage puts produed. Let α = A two input EXOR gate alulation β = A two input AD gate alulation δ= A OT gate alulation T = Total logial alulation The total logial alulation of the CSA presented in [15] and [17] are T= 8α+96β+δ and T=0α+8β+1δ respetively. On the ontrary, the total logial alulation of the presented CSAs in this study are T=37α+9β+1δ (Fig. 1) and T=3 α+3β+5δ (Fig 15). The presented CSAs require only 13 reversible gates whereas the CSA designs in [15] and [17] require 1 and reversible gates respetively. The presented designs also signifiantly redue the required number of onstant inputs and garbage puts. It should also be noted that the area onsumptions of the presented designs are minimum ompared to the designs found in the literature [15] [17]. Evaluation of the proposed designs an be omprehended easily with the help of the omparative results given in Table I. The optimum number of blok size, opt, of the presented CSAs is 8 for =16. On the ontrary, the number of bloks for the designs in [15] and [17] are frational and therefore impratial (lok size must be integer). Fig. 16 shows the adder size and the orresponding delay for different CSA implementations inluding those presented in this study. For 16, the proposed CSAs show better performane than the existing ounterparts. III. COCLUSIO This paper presents the effiient approahes for designing variable blok skip logi using parity preserving reversible gates that are minimized in terms of hardware omplexity, gate ount, onstant inputs and garbage puts. Tehnology independent evaluation demonstrates its superiority with the existing designs. The two new measures area onsumption (AC) and path delay (PD) has been taken into onsideration to evaluate all designs inluding those presented in this paper. REFERECES [1] R. Landauer, Irreversibility and heat generation in the omputing proess, IM J. Researh and Development, vol. 5, pp , [] C. H. ennet, Logial reversibility of omputation, IM J. Researh and Development, vol. 17, no. 6, pp , [3] M. S. Islam, M. R. Islam, M. R. Karim, A. A. Mahmud and H. M. H. abu, Variable blok arry skip logi using reversible gates, In Pro. of 10th International Symposium on Integrated Ciruits, Devies & Systems, Singapore, pp 9-1, 8-10 September, 00. [] M. S. Islam, M. R. Islam, M. R. Karim, A. A. M. and H. M. H. abu, Minimization of adder iruits and variable blok arry skip logi using reversible gates, In Pro. of 7th International Conferene on Computer and Information Tehnology, Dhaka, angladesh, 6-8 Deember, 00, pp [5] M. S. Islam and M. R. Islam, " Minimization of reversible adder iruits", Asian Journal of Information Tehnology, vol., no. 1, pp , 005. TALE I COMPARATIVE EXPERIMETAL RESULT OF DIFFERET FAULT TOLERAT CSA CIRCUITS CSA Design Gate Count Hardware Constant Garbage Area Complexity Inputs Outputs Consumption 1-bit FTFA [17] MIG 6α+β+δ bit FTFA [9][10] IG 8α+6β+δ bit FTFA [15] FRG 8α+16β+δ bit CSA: This study (Fig. 1) 8MIG+3FT+1FG+1FRG=13 37α+9β+1δ bit CSA: This study (Fig. 15) 8 MIG+ FRG+ 1FG =13 3 α+3β+5δ bit CSA[17] 8 MIG + FT + FG=1 0α+8β+1δ bit CSA [15] FRG 8α+96β+δ 19 7

9 CSA Presented TALE II This Study + CSA [17] CSA [15] T fixed AD T var iable OF DIFFERET CSA IMPLEMETATIOS T fixed opt T var iable t opt Fig. 16 Adder Size vs. Delay for different CSA implementations: Adder Size is plaed on horizontal axis and delay is plaed on vertial axis [6] M. S. Islam, M. M. Rahman, Z. egum and M. Z. Hafiz, "Low ost quantum realization of reversible multiplier iruit", Information Tehnology Journal, vol. 8, no., pp.08-13, 009. [7]. Parhami, Fault tolerant reversible iruits, in Proeedings of 0th Asimolar Conf. Signals, Systems, and Computers, Paifi Grove, CA, pp , Otober 006. [8] R. K. James, Shahana T. K., K. P. Jaob and S. Sasi, Fault Tolerant Error Coding and Detetion using Reversible Gates, IEEE TECO, pp. 1-, 007. [9] M. S. Islam, M. M. Rahman, Z. egum, M. Z. Hafiz and A. A. Mahmud, Synthesis of fault tolerant reversible logi iruits, In Pro. IEEE International Conferene on Testing and Diagnosis, Chengdu, China, 8-9 April, 009. [10] M. S. Islam and Z. egum, "Reversible logi synthesis of fault tolerant arry skip CD adder", angladesh Aademy of Siene Journal, vol. 3, no.,pp , 008. [11] R. Feynman, Quantum mehanial omputers, Optial ews, vol. 11, 1985, pp [1] E. Fredkin and T. Toffoli, Conservative logi, Intl. Journal of Theoretial Physis, pp , 198. [13] T. Toffoli, Reversible omputing, In Automata, Languages and Programming, Springer-Verlag, pp. 63-6, [1] A. Peres, Reversible logi and quantum omputers, Physial Review: A, vol. 3, no. 6, pp , [15] J. W. rue, M. A. Thornton, L. Shivakumaraiah, P.S. Kokate, X. Li, Effiient adder iruits based on a onservative reversible logi gates, In Proeedings of IEEE Computer Soiety Annual Symposium on VLSI, Pittsburg, PA, pp , 00. [16] M. Haghparast and K. avi, A novel fault tolerant reversible gate for nanotehnology based systems, Am. J. of App. Si., vol. 5, no.5, pp , 008. [17] M. S. Islam, M. M. Rahman, Z. egum, M. Z. Hafiz, Fault Tolerant reversible logi synthesis: arry look-ahead and arry-skip adders, In Pro. of IEEE International Conferene on Advanes in Computational Tools for Engineering Appliations, pp , July 15-17, 009. Md. Saiful Islam is Leturer in the Institute of Information Tehnology at the University of Dhaka., Dhaka-1000, angladesh. He holds MS degree in Computer Siene and Engineering from the University of Dhaka, 007. Mr. Islam has more than researh artiles published in several journals and onferenes. Mr. Islam also leads and teahes modules at both S and MS levels in Information Tehnology and Software Engineering. His researh interests inlude Reversible Logi Design, Multimedia Information Retrieval, Mahine Learning, Evolutionary Computing and Pattern Reognition. Muhammad Mahbubur Rahman reeived his master degree in Information Tehnology from Institute of Information Tehnology at University of Dhaka. Currently, he is working as a leturer in the department of Computer Siene at Amerian International University-angladesh. His researh interests inlude Data Mining, Mahine Learning, ioinformatis, Game Theory, Artifiial Intelligene, Eonometris and Logi Ciruit Minimization. Currently his ative researh works are in bioinformatis and data mining. He has several years of working experiene in loal and international teleommuniation and software ompanies. He is a founder and developer of a famous personalized searh engine, Dr. Zerina egum obtained her. S (Hons) and M. S in Physis from the University of Dhaka in1986 and 1987 respetively. Dr. egum started her arrier as a Researh Fellow in ose Researh Centre at University of Dhaka. Two years later she joined as a Programmer in the Computer Centre of the same university. She was awarded M. Phil for her researh in Semiondutor Tehnology and Computerized Data Aquisition System in She was repositioned as a Leturer in the entre in As reognition of her standing researh in organi semiondutor, Department of Physis, University of Dhaka awarded her with Ph. D. degree in 007. She is still ontinuing to serve University of Dhaka as a Professor in the Institute of Information Tehnology. Her urrent researh interest areas inlude Semiondutor Tehnology, Computerized Data Aquisition System, Advaned Digital Eletronis, Software Engineering and Computational iology. Dr. egum is looking forward to build up IIT as the vanguard of ICT eduation and researh in Sh Asia. Mohd. Zulfiquar Hafiz obtained his. S (Hons) and M. S in Pure Mathematis from the University of Dhaka in 1986 and 1987 respetively. Mr. Hafiz started his arrier as a programmer in the Computer Centre at University of Dhaka in He was repositioned as a Leturer in the entre in He is still ontinuing to serve University of Dhaka as an Assoiate Professor in the Institute of Information Tehnology. His urrent researh interest areas inlude Computer etworks, Embedded Systems and Computational Fluid Dynamis.