Power-speed Trade-off in Parallel Prefix Circuits
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1 Power-speed Trade-off in Parallel Prefix Ciruits ITCom 00 High-Performane Pervasive Computing Conferene Boston, MA July 9 August, 00 by S. Vanihayobon, S. K. Dhall, S. Lakshmivarahan, J. K. Antonio Shool of Computer Siene University of Oklahoma
2 Outline Overview of Prefix Ciruits Overview of Power Consumption in CMOS Ciruits Power Consumption Model for Prefix Ciruits Simulated Power Consumption for Prefix Ciruits Power-speed Trade-off for Prefix Ciruits Conlusions
3 Overview of Prefix Ciruits The prefix problem is to ompute y i = x x Lxi x i for i =,,, where denotes an assoiative binary operation Prefix iruits used in a number of areas, inluding arry-look-ahead adder ranking radix sort
4 Overview of Prefix Ciruits Struture and otation for a Prefix Ciruit input nodes ( x i = i 4 operation node level : : : :4 output nodes ( y i = : i
5 Overview of Prefix Ciruits Basi Definitions for Prefix Ciruits The iruit size is total number of operation nodes The iruit depth is the length of the longest path The iruit fan-in is the maximum fan-in of all nodes The iruit fan-out is the maximum fan-out of all nodes Known Lower Bounds for -Input Prefix Ciruits size depth size depth
6 Overview of Prefix Ciruits Comparison of Serial and Parallel Prefix Ciruits Serial Prefix Ciruit with size = and depth = level 4... : : : :4 input output Parallel Prefix Ciruit with size = 4 and depth = level 4... : : : :4 input output
7 Overview of Prefix Ciruits Prefix Ciruits Considered Serial Prefix Ciruit (S Divide and Conquer Parallel Prefix Ciruit (DC Ladner and Fisher Parallel Prefix Ciruit (LF, 980 Brent and Kung Parallel Prefix Ciruit (BK, 98 Snir Parallel Prefix Ciruit (S, 986 Lakshmivarahan, Yang and Dhall Parallel Prefix Ciruit (LYD, 994 Lin and Shin Parallel Prefix Ciruit (SL, 999
8 Overview of Prefix Ciruits Prefix Ciruit Size Depth Fan-out S( DC( ( ( BK( LF 0 ( 4 F (5 k ( k k LF k ( when k - S( depth max(, depth SL( depth 5 depth LYD( depth 6 depth
9 Overview of Power Consumption Soures of Power Consumption in CMOS Leakage Current Dynami Capaitane Charging Current Most important for CMOS Dependent on lok frequeny Dependent on signal ativity Transient Current
10 Overview of Power Consumption The power onsumption due to swithing is given by P swithing = ap eff V DD f V f DD apeff is the supply voltage is the lok frequeny is the effetive swithed apaitane, CL a f is the iruit load apaitane ap = a is the iruit swithing ativity fator* eff f C L *ote: without onsideration of glithing, with onsideration of glithing, it is possible to have > a f 0 a f
11 Overview of Power Consumption Examples to illustrate the effet of glithing, assume signals q, r, s, t are synhronously loked non-zero propagation delay at eah node load apaitane at eah node is 0 For eah iruit below, the load apaitane is C L = 0 ap eff = 6 = 6 0 = C L ap eff = 4 0 = (4/C L q r qr qrs s t q r s t qr st qrst (a Chained Implementation qrst (b Tree Implementation
12 Overview of Power Consumption Worst ase analysis Input signals ause node outputs to transition at every yle A node at level i experienes i transitions (inludes glithes Assuming onstant load apaitane 0 at eah node, then the effetive swithed apaitane of a iruit is ap eff depth = iw i= i 0 w i is number of nodes at level i
13 Power Consumption Model Load apaitane of node with fan-out of k is modeled by 0 (k ' 0 ' ' fan-out = k Calulation of effetive swithed apaitane for a prefix iruit divided into two parts ap ( = 0Kap ( ' Rap ( eff eff eff onstant part residual part
14 Power Consumption Model ap ( = 0Kap ( ' Rap ( eff eff onstant part Kap depth( ( = i= eff iw i w i is number of nodes at level i eff residual part Rap eff ( depth( = i k i= j= ( j w w ij is number of nodes at level i having fan-out equal to j ij
15 Power Consumption Model Example alulation of ap eff for the DC( iruit Kap eff ( = Kap eff ( = Kap eff depth IPUT DC DC : : :- : : OUTPUT
16 Power Consumption Model Example alulation of ap eff for the DC( iruit Rap eff ( = 0 Rap eff ( = Rap eff depth IPUT DC DC : : :- : : OUTPUT
17 Power Consumption Model Example alulation of ap eff for the DC( iruit ap ( = 0Kap ( ' Rap ( eff eff ap( Kap eff ( = eff = ( 0 ( 4 4 Kapeff ( = Kapeff ( depth( sd s sd s ' ap eff ( = 0 Rap eff ( = 0 s = size Rap ( eff = ( = Rapeff ( d = depth ( ( = ( ( ' eff
18 SL( S( LYD( LF k ( BK( DC( S( ' 0 ( ( ( ( ( ' 0 ( 4 ( 4 [ ] 0 ( ' ( ( ( k LF ' 0 ( 4 ( 4 [ ] 0 ( ' ( ( ] ( ( [ 0 ( ( ( ( ( ' ] ( [ 4 ( ( ( ( ( ' ( Ο ( Ο ( Ο ( Ο ( Ο ( Ο ( Ο ( ] ( ( [ 0 ( ( ( ( ( ' Power Consumption Model Value of ap eff for different prefix iruits
19 Simulated Power Consumption Parameter Values umber of inputs, = 8, 6,, 64 Binary operation is XOR gate Supply voltage, V DD =.8V Simulated power onsumption omputed by averaging power onsumption from many input vetors Simulated power onsumption ompared to analytial model for seven prefix iruits
20 Simulated Power Consumption Comparison of analytial model and simulation results for = Analytial Model.5 Simulation ormalized Power Consumption Power Consumption (W BK Snir SL LYD DC LF0 LF Serial 0.0 BK Snir SL LYD DC LF0 LF Serial Prefix Ciruit Prefix Ciruit
21 Simulated Power Consumption Comparison of analytial model and simulation results for parallel prefix iruits ormalized Power Consumption Analytial Model 8 bits 6 bits bits 64 bits Power Consumption (W Simulation 8 bits 6 bits bits 64 bits BK Snir SL LYD DC LF0 LF umber of Bits umber of Bits
22 Power-speed Trade-off Assuming the speed of a iruit to be inversely proportional to the iruit s depth is appropriate for omparing iruits with the same supply voltage However, saling the supply voltage an also be an effetive way of making a power-speed trade-off P swithing = ap Reduing voltage dereases power onsumption but generally inreases iruit delay eff V DD f
23 Power-speed Trade-off A.P. Chandrakasan and R. W. Brodersen, Low Power Digital CMOS Design, Kluwer Aademi Publishers, Depth BK Snir SL LYD DC LF0 LF Supply Voltage (V
24 Power-speed Trade-off Modified Depth-Based Delay Model (depth-based delay model saled with empirial delay measurements ormalized Delay Supply Voltage (V BK Snir SL LYD DC LF0 LF
25 Power-speed Trade-off Comparison of modified depth-based delay model and simulation results for = 64 ormalized Delay Modified Depth-Based Delay Model Supply Voltage (V BK Snir SL LYD DC LF0 LF Delay (us Simulation Supply Voltage (V BK Snir SL LYD DC LF0 LF
26 Power-speed Trade-off Power-Speed Trade-off Example Assume maximum aeptable delay is 6.4 µs Power redution of about.6 times an be obtained without speed loss by using LYD prefix iruit ompared with using the divide-and-onquer prefix iruit Power Consumption (W W Supply Voltage (V.44W BK Snir SL LYD DC LF0 LF Delay (us Supply Voltage (V BK Snir SL LYD DC LF0 LF
27 Conlusions Analytial power onsumption model was developed and applied to seven prefix iruits Auray of analytial power onsumption model verified with PSpie simulations Modified depth-based delay model proposed to aount for propagation delay dependeny on supply voltage value Example of power-speed trade-off design provided Future Work effet of pipelining on power-speed trade-off effet of fan-out on delay
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