EPC2053 Enhancement Mode Power Transistor

Transcription

1 Enhanement Mode Power Transistor V DS, V R DS(on), 3.8 mω I D, 8 G D S EFFICIENT POWER CONVERSION HL Gallium Nitride s exeptionally high eletron mobility and low temperature oeffiient allows very low R DS(on), while its lateral devie struture and majority arrier diode provide exeptionally low Q G and zero Q RR. The end result is a devie that an handle tasks where very high swithing frequeny, and low on-time are benefiial as well as those where on-state losses dominate. Maximum Ratings PRMETER VLUE UNIT Drain-to-Soure Voltage (Continuous) V DS Drain-to-Soure Voltage (p to, 5 ms pulses at 5 C) Continuous (T = 5 C) 8 I D Pulsed (5 C, T PULSE = 3 µs) 6 Gate-to-Soure Voltage 6 V GS Gate-to-Soure Voltage - T J Operating Temperature - to 5 T STG Storage Temperature - to 5 Thermal Charateristis PRMETER TYP UNIT R θjc Thermal Resistane, Juntion to Case.7 R θjb Thermal Resistane, Juntion to Board.7 R θj Thermal Resistane, Juntion to mbient (Note ) 53 V V C C/W Note : R θj is determined with the devie mounted on one square inh of opper pad, single layer oz opper on FR board. See for details. egan FETs are supplied in passivated die form with solder bumps. Die size: 3.5 mm x mm ppliations 8 V Servers Lidar/Pulsed Power Isolated Power Supplies Point of Load Converters Class D udio LED Lighting Low Indutane Motor Drive Benefits Higher Swithing Frequeny Lower swithin losses and lower drive power Higher Effiieny Lower ondution and swithing losses, zero reverse reovery losses Ultra Small Footprint - Higher power density Stati Charateristis (T J = 5 C unless otherwise stated) PRMETER TEST CONDITIONS MIN TYP MX UNIT BV DSS Drain-to-Soure Voltage V GS = V, I D =. m V I DSS Drain-Soure Leakage V DS = 8 V, V GS = V, T J = 5 C.7.3 m I GSS V GS = 5 V, T J = 5 C.3 m Gate-to-Soure Forward Leakage V GS = 5 V, T J = 5 C.7 9 m Gate-to-Soure Reverse Leakage # V GS = - V, T J = 5 C.3.3 m V GS(TH) Gate Threshold Voltage V DS = V GS, I D = 9 m.8..5 V R DS(on) Drain-Soure On Resistane V GS = 5 V, I D = mω V SD Soure-Drain Forward Voltage I S =.5, V GS = V.9 V # Defined by design. Not subjet to prodution test. EPC THE LEDER IN GaN TECHNOLOGY COPYRIGHT 9

2 Dynami Charateristis (T J = 5 C unless otherwise stated) PRMETER TEST CONDITIONS MIN TYP MX UNIT C ISS Input Capaitane # C RSS Reverse Transfer Capaitane V DS = 5 V, V GS = V C OSS Output Capaitane # C OSS(ER) Effetive Output Capaitane, Energy Related (Note ) 79 V DS = to 5 V, V GS = V C OSS(TR) Effetive Output Capaitane, Time Related (Note 3) 93 R G Gate Resistane.6 Ω Q G Total Gate Charge # V DS = 5 V, V GS = 5 V, I D = 5..8 Q GS Gate to Soure Charge Q GD Gate to Drain Charge V DS = 5 V, I D = 5.5 Q G(TH) Gate Charge at Threshold 3. Q OSS Output Charge # V GS = V, V DS = 5 V 5 68 Q RR Soure-Drain Reovery Charge # Defined by design. Not subjet to prodution test. Note : C OSS(ER) is a fixed apaitane that gives the same stored energy as C OSS while V DS is rising from to 5% BV DSS. Note 3: C OSS(TR) is a fixed apaitane that gives the same harging time as C OSS while V DS is rising from to 5% BV DSS.. pf nc Figure : Typial Output Charateristis at 5 C Figure : Transfer Charateristis 5ºC 5ºC V DS = 3 V ID Drain Current () R DS(on) Drain-to-Soure Resistane (mω) V GS = 5 V V GS = V V GS = 3 V V GS = V Figure 3: R DS(on) vs. V GS for Various Currents I D = I D = 5 I D = 37 I D = V DS Drain-to-Soure Voltage (V) V GS Drain-to-Soure Voltage (V) R DS(on) Drain-to-Soure Resistane (mω) ID Drain Current () 8 6 Figure : R DS(on) vs. V GS for Various Temperatures V GS Gate-to-Soure Voltage (V) V GS Gate-to-Soure Voltage (V) 5ºC 5ºC I D = 5 EPC THE LEDER IN GaN TECHNOLOGY COPYRIGHT 9

3 8 Figure 5a: Capaitane (Linear Sale) Figure 5b: Capaitane (Log Sale) 6 Capaitane (pf) 8 6 C OSS = C GD + C SD C ISS = C GD + C GS C RSS = C GD Capaitane (pf) C OSS = C GD + C SD C ISS = C GD + C GS C RSS = C GD V DS Drain-to-Soure Voltage (V) V DS Drain-to-Soure Voltage (V) Q OSS Output Charge (nc) Figure 6: Output Charge and C OSS Stored Energy E OSS C OSS Stored Energy (µj) V GS Gate-to-Soure Voltage (V) 5 3 Figure 7: Gate Charge I D = 5 V DS = 5 V V DS Drain-to-Soure Voltage (V). 6 8 Q G Gate Charge (nc) Figure 8: Reverse Drain-Soure Charateristis. Figure 9: Normalized On-State Resistane vs. Temperature I SD Soure-to-Drain Current () 5 5 5ºC 5ºC V GS = V Normalized On-State Resistane R DS(on) I D = V GS = 5 V V SD Soure-to-Drain Voltage (V) T J Juntion Temperature ( C) EPC THE LEDER IN GaN TECHNOLOGY COPYRIGHT 9 3

4 . Figure : Normalized Threshold Voltage vs. Temperature.3 I D = 9 m Normalized Threshold Voltage T J Juntion Temperature ( C) Figure : Transient Thermal Response Curves ZθJB, Normalized Thermal Impedane... Duty Fators: Single Pulse Juntion-to-Board Notes: Duty Fator = t p /T Peak T J = P DM x Z θjb x R θjb + T B t p - Retangular Pulse Duration (s) P DM t p T ZθC, Normalized Thermal Impedane.. Duty Fators: Juntion-to-Case Notes: Single Pulse Duty Fator = t p /T Peak T. J = P DM x Z θjc x R θjc + T C t p - Retangular Pulse Duration [s] P DM t p T EPC THE LEDER IN GaN TECHNOLOGY COPYRIGHT 9

5 Figure : Safe Operating rea I D - Drain Current () Limited by R DS(on) Pulse Width ms μs μs.. V DS - Drain-Soure Voltage (V) T J = Max Rated, T C = +5 C, Single Pulse TPE ND REEL CONFIGURTION mm pith, 8mm wide tape on 7 reel d e f g Loaded Tape Feed Diretion 7 reel a b 53 YYYY ZZZZ Die orientation dot Gate solder bar is under this orner (note ) Dimension (mm) target min max a b (see note) d e f (see note) g Die is plaed into poket solder bar side down (fae side down) Note : MSL (moisture sensitivity level ) lassified aording to IPC/JEDEC industry standard. Note : Poket position is relative to the sproket hole measured as true position of the poket, not the poket hole. DIE MRKINGS 53 Pin indiator YYYY ZZZZ Part Number Part # Marking Line Laser Markings Lot_Date Code Marking line Lot_Date Code Marking Line 3 53 YYYY ZZZZ EPC THE LEDER IN GaN TECHNOLOGY COPYRIGHT 9 5

6 DIE OUTLINE Solder Bump View 3 8 e B DIM MICROMETERS MIN Nominal MX B d 5 e d 6 5 Pad is Gate; Pads, 3,, 9,,,, 7, 8, 9,, 5, 6, 7, 8 are Soure; Pads 5, 6, 7, 8, 3,, 5, 6,,, 3, are Drain. Side View 685 +/ Seating Plane +/- RECOMMENDED LND PTTERN (units in µm) e d B DIM MICROMETERS 35 B 95 5 d 5 e 3 f 5 Pad is Gate; Pads, 3, 7, 8, 9 are Soure; Pads, 5, 6 are Drain. RECOMMENDED STENCIL DRWING (measurements in µm) g e d B Reommended stenil should be mil ( µm) thik, must be laser ut, opening per drawing. The orner has a radius of R6. Intended for use with SC35 Type solder, referene 88.5% metals ontent. dditional assembly resoures available at Effiient Power Conversion Corporation (EPC) reserves the right to make hanges without further notie to any produts herein to improve reliability, funtion or design. EPC does not assume any liability arising out of the appliation or use of any produt or iruit desribed herein; neither does it onvey any liense under its patent rights, nor the rights of others. egan is a registered trademark of Effiient Power Conversion Corporation. EPC Patent Listing: ep-o.om/ep/boutepc/patents.aspx Information subjet to hange without notie. Revised Marh, 9 EPC THE LEDER IN GaN TECHNOLOGY COPYRIGHT 9 6