OPTIMAL DESIGN AND SYNTHESIS OF FAULT TOLERANT PARALLEL ADDER/SUBTRACTOR USING REVERSIBLE LOGIC GATES. India. Andhra Pradesh India,

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1 OPTIMAL DESIGN AND SYNTHESIS OF FAULT TOLERANT PARALLEL ADDER/SUBTRACTOR USING REVERSIBLE LOGIC GATES S.Sushmitha 1, H.Devanna 2, K.Sudhakar 3 1 MTECH VLSI-SD, Dept of ECE, ST. Johns College of Engineering and Technology, Kurnool, Andhra Pradesh, India. 2 Assistant Professor, Department Of ECE,ST.Johns College of Engineering and Technology, Kurnool, Andhra Pradesh India, 3 H.O.D,Associate Professor, Dept of ECE, ST.Johns College of Engineering and Technology,Kurnool, AndhraPradesh,India. ABSTRACT: Reversible logic is most popular concept in energy efficient computations and this will be demand for upcoming future computing technologies. Reversible logic is emerging as an important research area and it will be having wide applications in many fields such as optical information processing, quantum computing and Low power CMOS design. Under ideal conditions, the reversible logic gates will produce zero power dissipation. So this concept will helpful for Low power VLSI design. Reversible logic has applications in Low Power VLSI, Quantum Computing, Nanotechnology and Optical computing. This paper proposes the design of an optimal fault tolerant Full adder/ Full subtractor. For this logic circuit input parity and output parity is same hence it is called parity preserving circuit. The proposed method require less complexity, less hardware, minimum number of gates, minimum number of garbage inputs and minimum number of constant inputs than existing methods. The design is implemented and synthesized by using Xilinx ISE 14.3 with Verilog coding and is simulated with Isim simulator. Keywords: Adder/Subtractor, Parity preserving reversible gates, Parallel Adder/Subtractor, Reversible logic gates. I. Introduction Today s new technology offers faster, smaller and complex circuits. Moore s law states that Performance (speed) of an integrated circuit per unit cost increased by a factor two for every 18 months. In order to achieve higher speed the clock frequency must be high and for smaller, complex circuit s the number of transistors in the IC must be large and they are more closely packed in order to save area. As the IC will be faster, complex means that will increases the power dissipation in the circuit. Almost all conventional computers comprises of million numbers of gates that are irreversible in nature. During logical operations in the circuit some information is erased or lost that will causes heat dissipation and energy loss. In electronics hardware designing energy dissipation is one of the most important aspects. The concept of reversibility in digital circuits is firstly related to energy by Landauer in 1961 who stated that there is small amount of heat Page No:231

2 dissipation the circuit due to loss of one bit of information and it would be equal to ktln2 where k is Boltzman constant and T is the temperature. Also in 1973 it was proved by Bennett that the energy ktln2 would not be dissipate from the circuit if input can be extracted from output and it would be possible if and only if reversible gates are used. A circuit will be reversible if input vector can be specifically retrieved from output vectors and here is one to one correspondence between input and output. Thermodynamics explain the concept of reversibility which taught the benefits of reversibility over irreversibility. Reversible logic synthesis of reversible combinational logic differs from sequential logic in that the output of the logic device depends on the present input unlike sequential circuits in which output depends on present as well as past input too. Addition is one of the essential operations in multiplication and division algorithms. It plays a vital role in many applications like DSP processors, Micro processors and in computing devices. Hence, it is required to design fast adder. But it is not possible to design a fast adder with normal Full adders or half adders which are made with normal logic gates which are poor in the performance Parameters like gate delay or any and which are also less fault tolerant. To overcome the drawbacks of the existing designs a novel design of reversible optimized fault tolerant Full adder/ Full subtractor is proposed here the fault tolerant circuits are parity preserving reversible logic gates which are better than conventional logic it is not possible and It is one of distinct feature of reversible logic. Reversible Function: A multiple output Boolean function (x1: x2: xn) of n Boolean variables is called as reversible if 1) The number of outputs is equal to number of inputs. 2) If reversible function performs permutations of set of input vectors. REVERSIBLE LOGICS Reversible Gates are the circuits in which number of outputs is equal to the number of inputs and there is a one to one mapping between the vector of inputs and outputs. It helps to determine the outputs from the inputs as well as helps to uniquely recover the inputs from the outputs. There are 3 important parameters are there for any Reversible gates those are Constant Inputs This refers to number of inputs that has to be maintained constant at 1 or 0 in order to synthesize the given logical function Garbage Outputs Garbage Outputs indicates the number of outputs which are not used in the synthesis of a given function. In certain cases these become mandatory to attain reversibility. The output that is added to an n x k function to make it reversible is called as garbage output. The following simple formula shows the relation between constant inputs and garbage outputs : (Input + Constant inputs) = (Output + Garbage Outputs). Quantum Cost Quantum cost may be defined as the cost of the circuit in terms of the cost of a primitive gate. It is Page No:232

3 calculated by the number of primitive reversible logic gates (1*1 or 2*2) required to realize the circuit. The quantum cost of a circuit is the minimum number of 2*2 unitary gates to represent the circuit keeping the output unchanged. The quantum cost of a 1*1 gate is 0 and that of any 2*2 gate is the same, which is 1. and outputs are given by P = A ; Q = A ^ B ; R = A ^ C ; Quantum cost of a Feynman double gate is 2. II. Related work The fault tolerant reversible gates are special gates in reversible gates. The fault tolerant gates satisfies the property of parity preserving i.e., the parity of input and output is same. A logic block is called parity preserving if every gate in that is parity preserving. Fault tolerance is the property that will enables the system to continue its operation properly when failure occurs in any of the component. If the system will be made up using fault tolerant components then the error detection and correction process will much easier. In communication and other systems fault tolerance is achieved by parity. Parity checking is most widely used method for error detection in digital logic circuits. It will most commonly used in arithmetic and other processing systems because those systems do not preserve the parity of the data, there have been attempts at performing arithmetic operations on specially. III. Proposed Work A. Feynman Double Gate Feynman Double gate is also one of the basic reversible logic gate with 3 inputs and 3 outputs also represented as 3*3 gate. It is depicted in Fig. 1. The inputs are denoted by I (A, B, C) and outputs are denoted by O (P, Q, R).The relation between inputs Figure 1: Feynman Double gate B. Fredkin Gate Fredkin gate is also one of the basic gate of reversible logic gate with 3 inputs and 3 outputs and denoted by 3*3 gate. It is depicted in Fig. 2. The inputs are denoted by I (A, B, C) and outputs are denoted by O (P, Q, and R). For Fredkin gate the quantum cost is 5. The relationship between inputs and outputs is given by P = A ; Q = A B ^AC ; R = A C ^ AB ; Figure 2: fredkin Gate A full adder is a combinational circuit that adds 3 input bits and produces 2 outputs. In the 3 input bits 2 bits are data bits and other bit is previous stage carry. The 3 input variables are denoted by A, B and Cin. The outputs sum and carry are denoted by S and Cout. The mathematical equation representing the full adder is A+B+Cin. A full subtractor is a combinational circuit that subtracts 2 input bits from first input and produces 2 outputs. In the 3 input bits 2 bits are data bits and other bit is present stage borrow. The 3 input variables are denoted by A, B and Cin (for convenience purpose present stage borrow is denoted by Cin ). The outputs Difference Page No:233

4 and Borrow are denoted by D and Bout. The mathematical equation represents full subtractor is A- B-Cin. The Boolean expressions of Full Adder / Full Subtractor are Figure 3: Symbol Of Full Adder / Full Substractor Design of optimal fault tolerant Full adder / Full subtractor The circuit diagram of optimal fault tolerant Full adder / Full subtractor is shown in Fig. 4. It contains F2G-1, F2G-2, F2G-3 and one Fredkin gate. For the first Feynman double gate (F2G-1) the inputs are B and A and one constant input 0. By using this first Feynman double gate we are duplicating the B input and A_B is generated. One B output act like garbage output (G1). For second Feynman double gate (F2G-2) the inputs are C and 2 constant inputs 0. Figure 4: Optimized Parity Preserving Full Adder / Full Substractor The second Feynman double gate (F2G-2) is used to triplicate the Cin. For this purpose Cin, 0, 0 are applied as inputs to second Feynman double gate (F2G-2) and it produces all outputs as Cin. Among three outputs one of the Cin acts like garbage output (G2). For third Feynman double gate (F2G-3), the inputs are A^B i.e., output of first Feynman double gate (F2G-1), Cin i.e., output of second Feynman double gate (F2G-2) and one constant input 0 then the outputs are A^B (garbage output G3), A^B^Cin i.e., SUM / DIFFERENCE and A^B. The A^B (output of third Feynman double gate (F2G- 3)), Cin (output of second Feynman double gate (F2G-2)), B ( output of first Feynman double gate (F2G-1)) are applied as inputs to the Fredkin gate. The outputs are A^B (garbage output G4), BORROW out and CARRY out. The symbol of Optimized Parity Preserving Full Adder / Full Substractor is shown in Fig. 5. Page No:234

5 Figure 5: Symbol of Optimized Parity Preserving Full Adder / Full Substractor Modified IG Gate (MIG): Fig. 6 shows 4*4 Modified IG gate. It has A, B, C and D input vector and output vector as P = A, Q = A B, R = AB C and S = AB D. Truth table of MIG gate Figure 6: Modified IG Gate (MIG) IV. Methodology We have studied adder design using reversible gates by several authors. Some authors are demonstrated that a reversible adder circuit can be realized with at least two garbage output and one constant input. For designing fault tolerant adder circuits these requirements are not applicable. Because in fault tolerant circuits the input parity must matches with the output parity. In the below section first we discuss fault tolerant half adder/subtractor design and after that fault tolerant full adder/subtractor design because the design full adder requires half adder circuit. The proposed design will work singly a unit which consists of both adder and subtractor. The design will consists of control line ctrl which will selects adder or subtractor according the control logic input. Page No:235

6 Figure 7: Reversible Fault Tolerant Half Adder/Subtractor circuit The fault tolerant half adder/ subtractor is realized using one Modified IG (MIG) gate and one Fredkin gate (FRG) shown in Fig. 7. The design will be having two inputs A & B and a control line ctrl which will controls mode of operation i.e. when ctrl is at logic 0, the circuit will acts as half adder and when ctrl is at logic 1, the circuit will acts as half subtractor. The S/D in Fig. 3 represent sum & difference line.the C/B in Fig. 7 represents carry & borrow line. The Fig. 8 represents the Fault Tolerant Half Adder/Subtractor (FT_HA/S) circuit with two constant inputs are forced at logic 0 and three garbage bits g1 to g3. As per conventional approach for designing reversible full adder it requires two half adders. So the fault tolerant reversible full adder/subtractor (FT_FA/S) circuit is built using two fault tolerant half adder/subtractor (FT_HA/S) circuits. The fault tolerant Full adder/ subtractor is realized using Two Modified IG (MIG) gate, two Fredkin gate (FRG) and one Feynman double gate (F2G) is shown in Fig. 9. The circuit will be having three inputs A, B & Cin (For full subtractor A, B & Bin are inputs) and a control line ctrl which will controls mode of operation i.e. when ctrl is at logic 0, the circuit will acts as full adder and when ctrl is at logic 1, the circuit will acts as full subtractor. Figure 9: Reversible Fault Tolerant Full Adder/Subtractor circuit Figure 8: Fault Tolerant Half Adder/Subtractor circuit (FTHA_S) Figure 10: Fault Tolerant Full Adder/Subtractor circuit (FT_FA/S) The Fig. 10 represents the Fault Tolerant Full Adder/Subtractor (FT_FA/S) circuit with Five constant inputs are forced at logic 0 and Seven garbage bits g1 to g7. Page No:236

7 Parallel Adder/Subtractor The n-bit Parallel adder/subtractor can be realized by cascading n number of full adder/subtractor. The carry/borrow from one full adder/subtractor will be propagated to the next full adder/subtractor. In this type of adder/subtractor the inputs are presented simultaneously (parallel) therefore these adder/subtractor arte called Parallel Adder/Subtractor. RTL schematic: Figure 11: Reversible Fault Tolerant n bit Parallel Adder/Subtractor The Fig.11 shows fault tolerant n-bit parallel adder/subtractor with a control line ctrl that will controls the mode of operation i.e. when ctrl is at logic 0, the circuit will acts as parallel adder and when ctrl is at logic 1, the circuit will acts as parallel subtractor. V. RESULTS Technology schematic Block diagram: Comparison Table: Existing system Proposed system Area(luts) Delay(ns) Power(W) Page No:237

8 CONCLUSION This paper presents efficient approach for the design of fault tolerant full adder/subtractor and parallel adder/subtractor. The proposed design can work as single unit that can acts as adder as well as subtractor depending upon our requirement. The proposed design offers less hardware complexity, less gate count, less garbage bits and constant inputs. The reversible computation can be done efficiently with less number of garbage bits and constant inputs. The proposed Fault tolerant Adder/Subtractor design can be used to realize some arithmetic components such as carry save adder, carry skip adder and multiplier/divisors etc,. In future we are planning to design more optimized Fault tolerant Adder/Subtractor design and other fault tolerant circuits i.e. less garbage bits and constant input. REFERENCES [1] R. Landauer, Irreversibility and Heat Generation in the Computational Process, IBM Journal of Research and Development, 5, pp , [2] C.H. Bennett, Logical Reversibility of Computation, IBM J. Research and Development, pp , November [3] M. S. Islam, and M. Rafiqul Islam, Minimization of reversible adder circuits, Asian Journal of Information Technology, vol. 4, no. 12, pp , [4] B. Parhami, Fault tolerant reversible circuits, in Proceedings of 40th Asimolar Conf. Signals, Systems, and Computers, Pacific Grove, CA, pp , October [5] D. Maslov, G. W. Dueck, and D. M. Miller, Synthesis of Fredkin Toffoli reversible networks IEEE Trans. VLSI Systems, vol. 13, no. v6, pp , [6] R. Feynman, Quantum mechanical computers, Optical News, vol. 11, 1985, pp [7] A. Peres, Reversible logic and quantum computers, Physical Review: A, vol. 32, no. 6, pp , [8] T. Toffoli, Reversible computing, In Automata, Languages and Programming, Springer-Verlag, pp , [9] E. Fredkin and T. Toffoli, Conservative logic, Intl. Journal of Theoretical Physics, pp , [10] P.Kaur and B.Dhaliwal,Design of Fault Tolearnt Full Adder=Subtarctor Using Reversible Gates, in Computer communication and Informatics (ICCCI), 2012 International Confrence on, Jan 2012, PP [11] Saligram, R.; Rakshith, T.R.,Design of Low Logical Cost Adders using Novel Parity Conserving Toffoli Gate, in Emerging Trends in Communication, Control, Signal Processing and Computing Applications (C2SPCA), 2013 International Conference on, vol., no., pp.1-6, Oct [12] Md, Saiful Islam et.al, Synthesis of Fault Tolerant Rveresible Logic Circuits, IEEE [13] J. W. Bruce, M. A. Thornton, L. Shivakumaraiah, P.S. Kokate, X. Li, Efficient adder circuits based on aconservative reversible logic gates, In Proceedings of IEEE Computer Society Annual Symposium on VLSI, Pittsburg, PA, pp , [14] H.R.Bhagyalakshmi and M.K.Venkatesha,An improved design of a multiplier using reversible logic gates, Intl. Journal of Engineering Science and Technology, Vol. 2(8), 2010, pp Page No:238

9 BIOGRAPHIES H.Devanna is an Assistant Professor in Department of ECE,in St.Johns college of Engineering and Technology,Yerrakota,Andhra Pradesh. S.Sushmitha is a PG Scholar,in VLSI,from St.Johns college of Engineering and Technology,Yerrakota,Kurnool,AndhraPradesh. Page No:239