ISSN Vol.03, Issue.03, June-2015, Pages:

Transcription

1 ISSN Vol.03, Issue.03, June-2015, Pages: Design of Low Power Arithmetic and Logic Unit using Reversible Logic Gates LAKSHMIKANTHA MN 1, ANURADHA MG 2 1 Dept of ECE (VLSI Design & ES), JSS Academy of Technical Education, Bangaluru, India, lakshmikantha.02mn@gmail.com. 2 Dept of ECE, JSS Academy of Technical Education, Bangaluru, India, Anuarun.19@gmail.com. Abstract: Reversible logic has great attention in recent years due to ability to reduce the power dissipation which is main requirement in low power design. Arithmetic Logic Unit (ALU) is one of the most crucial components of any system and is used in many appliances like calculators, cell phones, and computers and so on. But the ALU which are designed using non reversible logic gates consume more power. So there is a need for lesser power consumption the reversible logic technique helps in reducing power consumption. This paper presents an implementation of ALU based on reversible logic to reduce power consumption during operations. The design is implemented using Xilinx 9.1 tool and GPDK 180nm Cadence RTL Compiler. Power and timing analysis are done and compared with the non reversible logic ALU. The implemented design shows 0.781μw power reduction and mm 2 Area reduction for 16 bit reversible logic based Arithmetic and logic unit compared to non reversible logic based Arithmetic and logic unit. Keywords: Reversible Logic Gates, Garbage Output, Toffoli Gate, Peres Gate, Verilog, Feynman Gate. I. INTRODUCTION Energy loss is a very important factor in modern VLSI design the Irreversible hardware computation results in energy dissipation due to information loss. R.Landauer [1] has shown that for irreversible logic computations, each bit of information loss generates KTln2 joules of heat energy, where K is Boltzmann s constant and T is the temperature at which computation is performed. Reversible logic circuit does not loss of information and reversible computation in a system can be performed only when the system consists of reversible gates. C.H.Bennet [2] showed that KTln2 joules energy dissipation would not occurs if circuit computation is carried out in a reversible way. A circuit is said to be reversible if the input vector can be uniquely recovered from the output vector and there is a one to one correspondence between its input and output assignments.thus, the number of inputs and outputs in reversible logic circuits are equal. Reversible logic has applications in several technologies such as nanotechnology, DNA computing, low power design, optical computing and quantum computing[3]. It is not possible to construct quantum circuits without reversible logic gates. Synthesis of reversible logic circuits is significantly more complicated than the traditional irreversible logic circuits because in a reversible logic circuit fan-out and feedback are not allowed. The key point of reversible computing is that the electric charge on the storage cell consisting of transistors is not permitted to flow away when the transistor is switched. Then it can be reused through reversible computing, which can decrease the energy consumption. When there is no loss of information bits, then the system is reversible. II. BASIC REVERSIBLE GATES A reversible logic gate is an n-input, n-output device indicating that it has same number of inputs and outputs. A circuit that is built from reversible gates is known as reversible logic circuit. This prevents the loss of information which is the root cause of power dissipation in irreversible logic circuits. In the design of reversible logic circuits the following points must be considered to achieve an optimized circuit. They are Fan-out is minimum Loops or feedbacks are not permitted Minimum delay Minimum quantum cost. Reversible gate is realized by using 1*1 NOT gates and 2*2 Reversible gates, such as V, V+ (V is square root of NOT gate and V+ is its hermitian) and FG gate which is also known as CNOT gate. The V and V+ Quantum gates have the property given in the Equations (1, 2 and 3). V * V = NOT (1) V * V+ = V+ * V = I (2) V+ * V+ = NOT (3) The Quantum Cost of a Reversible gate is calculated by counting the number of V, V+ and CNOT gates. A. Not Gate The Reversible 1X1gate is NOT Gate with zero Quantum Cost is as shown in the Figure 1. Figure1. Reversible NOT gate IJVDCS. All rights reserved.

2 B. Controlled NOT gate The Reversible 2X2 gate with Quantum Cost of one having mapping input (A, B) to output (P = A, Q= A B) is as shown in the Figure 2. LAKSHMIKANTHA MN, ANURADHA MG Q =A B AC, R= AB A C ), where A, B, C are the inputs and P, Q, R are the outputs, respectively the Quantum cost of Fredkin gate is 5. Figure 5 shows a 3X3 Fredkin gate. Figure2. Reversible Feynman/CNOT gate. Here A is the controlling signal when A=0 the output of Q=B and A=1 the output of Q=NOT(B) C. Toffoli Gate The Reversible 3X3 gate with three inputs and three outputs. The inputs (A, B, C) mapped to the outputs (P=A, Q=B, R=A.B C) is as shown in the Figure.3. Toffoli gate is one of the most popular Reversible gates and has Quantum Cost of 5. Figure5. Reversible Fredkin gate. F. Double Peres Gate (DPG) DPG gate is achieved by cascading two 3X3 Peres gate. The quantum realization cost of this gate is 6. Since it includes two 3X3 Peres gates. The gate can work singly as a reversible full adder circuit when its fourth input is set to zero (D = 0) as shown in Figure 6. Figure6. Reversible Dperes gate Figure3. Reversible Toffoli gate. Here AB are the controlling signals when AB=0 the output of R=C and AB=1 the output of R=NOT(C). D. Peres Gate It is a 3*3 Peres gate.the input vector is I (A,B, C) and the output vector is O (P, Q, R). The output is defined by P = A, Q = A B and R = AB C. Quantum cost of a Peres gate is 4. Figure 4 shows a 3X3 Peres gate. Figure 4: Reversible Peres gate E. Fredkin Gate Fredkin gate is a 3X3 reversible logic gate with three inputs and three outputs.the Fredkin gate maps (A, B, C) to (P = A, III. DESIGN OF ARITHMETIC LOGIC UNIT Arithmetic and logic unit (ALU) is a data processing unit which is an important part of CPU. There are various types of CPUs are available but every CPU contains an ALU. ALU can implement in many different ways like reversible, irreversible, pass transistor logic and etc. The design is in different ways but operation is same arithmetic and logical operations. In this paper two types of ALU are implemented using Reversible logic gates Reversible ALU using all Reversible gates Reversible ALU using Toffoli logic gate IV. REVERSIBLE ALU USING ALL REVERSIBLE GATES In this paper, the multi-function ALU based on reversible logic gates has been designed which contains the reversible control unit and the reversible full adder. The reversible control unit and the reversible full adder are cascaded and arbitrary bit reversible ALU modules can be realized by this way. Here 1bit ALU has been designed. The A and B inputs of the reversible control unit are altered depending on the S0, S1and S2 values and applied as input to reversible full adder using DPeres gates. By controlling one of the inputs to adder, various arithmetic and logic operations can be realized. The designed circuit has three control signals with a provision for realizing eight arithmetic operations and four logic operations. Figure7 shows the block diagram of 1bit reversible ALU

3 Design of Low Power Arithmetic and Logic Unit using Reversible Logic Gates Table1. 1-Bit Function Operation Table Figure7. Block diagram of 1bit reversible ALU. A. Reversible control unit Reversible control unit has 9 reversible gates (3 NOT gate, 2 CNOT gate, 2 Fredkin gate, 1 3x3 Toffoli gate, 1 4x4 Toffoli gate). The complete control unit with reversible logic gate can be realized as in Figure 7.1 V. REVERSIBLE ALU USING TOFFOLI GATE The reversible ALU can implement by using 3*3 toffoli logic gate The multi-function ALU based on reversible toffoli logic gates mainly contains the reversible function generator (FUNC) and the reversible controlled unit (DXOR). The reversible function generator and the reversible controlled unit are cascaded by some n-toffoli gates and NOT gates, and arbitrary bit reversible ALU modules can be realized by this way. In the procedure of cascading the reversible function generator and the reversible controlled unit, we reuse the output signals to reduce the cost of circuit design as much as possible. A. Reversible Function Generator The function generator feature is to process the input information Ai and Bi under the control of the parameters S0, S1, S2 and S3, and then we will get the combined functions Xi and Yi at the output side, where Xi is the combined Figure7.1. Block diagram of Reversible control unit. The designed circuit has three control signals with a provision for realizing eight arithmetic Operations and four logic operations. Three control variables S2, S1, S0 along with Cin select twelve different arithmetic-logic operations and the S2 distinguishes between arithmetic and logic operations. The A and B inputs are altered depending on the S0, S1and S2 values and applied as input to full adder using DPeres gates. Full adder is the fundamental building block in many computational units. The design of Reversible full adder as shown in fig 6 the outputs of control unit is given to the inputs of the full adder. Depending on the values of s2, s1, s0 & cin we can get different arithmetic & logical operations on fun & cout output signals. where G0 to G7 are the garbage outputs which are not used in further operation. All the arithmetic & logical operations are shown in Table1. Figure8. Reversible Function Generator. Figure8.1. The Package diagram of Reversible Function Generator.

4 function on Ai and Bi controlled by the parameters S3 and S2 and Yi is the combined function on Ai and Bi controlled by the parameters S1 and S0. The reversible function generator is shown in Figure 8 and its corresponding package diagram is shown in Figure 8.1. The Function generator is design by using 8 toffoli gate Ai and Bi are the inputs of the function generator and R0,R1,R2,R3 are the additional outputs which are used as a control parameters of next function generator to reduce the cost of the circuit design B. Reversible DXOR gate The Reversible DXOR gate process the complete sum of three inputs, the output Fi=P xor Q xor cin where P = Xi Q=Yi. That is to say, let the combined functions Xi and Yi from the reversible function generator add the carry signal Ci to get the final result Fi. The below given figure 9.2 shows the reversible DXOR gate LAKSHMIKANTHA MN, ANURADHA MG signal Cout and the garbage outputs. In addition the outputs R0, R1, R2 and R3 of reversible function generator FUNC0 are respectively seen as the inputs S0, S1, S2 and S3 of reversible function generator FUNC1 and so on. The value of the first and the second inputs of reversible DXOR0 DXOR15 are equal to the value of outputs Xi and Yi of function generator FUNC0 FUNC15. The value of the third input Ci of reversible DXOR0 DXOR15 have some connection with the control signal M. Their relationship can be expressed as follows: When i = 0 then When i= 1 then When i>2 then (4) (5) (6) Figure 8.2: The package diagram Reversible DXOR gate. The Reversible DXOR gate design can be done by cascading the two controlled NOT gate Figure8.3. Reversible DXOR gate. C. The realization of Reversible 16bit ALU To design the reversible 16bit ALU with the minimum cost, we used 3*3 Toffoli gates and NOT gates to cascade the reversible function generator and the reversible DXOR gate. The reversible ALU in Figure 8.4 is cascaded by reversible function generators, reversible DXOR gate and 3*3 Toffoli gates. The reversible ALU performs operations on to binary numbers A = (A15,...A0) and B = (B15, B0). In Figure 8.4, the first operand A, the second operand B, the control signals S0 to S3, the low carry signal Ci and the control signal M are reversible ALU s input signal, while the result, Fun = (F15,...F0), the carry output Figure 8.4: The design of N bit Reversible ALU The outputs of the function generator Xi and Yi are generated. when the inputs signals Ai and Bi are applied under control parameters these output signals a given to the DXORi respectively and also make operation with control signal M to get the third input signal Ci of reversible DXORi based on the equation 4 to 6. VI. RESULTS The results consists of three parts 1 st part is the simulation results obtained from Xilinx ISE 9.1 version 2 nd part is the synthesis results obtained from Cadence RTL compiler for 180nm technology 3 rd part is power and area comparison of reversible and irreversible ALU.

5 Design of Low Power Arithmetic and Logic Unit using Reversible Logic Gates Figure 9.1:Simulation waveform of 1bit ALU. The figure 9.1 shows the 1bit arithmetic and logic operation in The results inputs A=1,B=0 and the control parameter S=0000 The S2 is 0 so its performed the arithmetic operation and output fun= transfer A in simulation results the fun=1.and when control parameter S=100x the S2 is 1 so it performed Logic operation and the output fun=(a or B) =1. The design of reversible 16bit ALU using toffoli gate are designed by verilog code and also verify the arithmetic and logic function according to the below given function table 2 The Verilog code is synthesized using cadence RTL compiler for the area, power and delay analysis. The table 3 shows the area power and delay analysis report of 1bit,4bit,8bit and 16bit reversible ALU. Table 3: Area, Power, Delay Analysis of Reversible ALU Figure9.2. Simulation waveform of 16bit ALU. The marked example in the figure9.2 are explained in the below The figure 9.2 shows the 16bit arithmetic and logic operation here inputs A= , B= and control signals M=1, Cin=0 control parameter S=0011 it performed logic operation because M=1 and the output function=0 in simulation results fun= when control signals M=0, cin=1 control parameter S=0111. Its performed arithmetic operation because the M=0 and cin=1. The output fun=(ab 1)= In waveform I shown in hex decimal number fun=1554h. Table2. 16 Bit Reversible Function Table In this table consists of 16 arithmetic and 16 logic operations and the control parameters selects the all function of operation under the control input signals M and Cin. The Table 4 shows power and area analysis of reversible and irreversible 4bit and 16bit ALU. The irreversible ALU is designed to performed the same functionality operations as that of reversible ALU. the comparison results shows that the reversible logic ALU consumes less power and Area this can be shown in table4.

6 Table4. Area and power analysis of reversible and irreversible ALU The layouts of reversible ALU are generated by using the Cadence Encounter. The given figure 9.3 shows the 16bit reversible ALU LAKSHMIKANTHA MN, ANURADHA MG [2] C.H. Bennett, Logical reversibility of computation, IBM J. Research and Development, vol. 17, pp , Nov [3] W. N. Hung, X. Song, G.Yang, J.Yang, and M. Perkowski, Optimal synthesis of multiple output boolean functions using a set of quantum gates by symbolic reachability analysis, IEEE Trans. Computer-Aided Design, vol. 25, no. 9, pp , Sept [4] Zhijin Guan, Wenjuan Li, Weiping Ding, Yueqin Hang, and Lihui Ni, An Arithmetic Logic Unit Design Based on Reversible Logic Gates, IEEE Pacific Rim Conference on Communications, Computers, and Signal Processing, 2011, DOI: /PACRIM , pp [5] Madhusmita Mahapatro, M.Suresh, Panda S.K, Saheel M, Panda A.K, and Shukla M.K, Design of Arithmetic Circuits Using Reversible Logic Gates and Power Dissipation Calculation, International Symposium on Electronic System Design (ISED), 2010, DOI: /ISED , pp [6]T.Toffoli.Reversible computing, Tech mem MIT/LCS/ TM-151, MIT Lab for Comp.Sci,1980. [7] E.Fredkin, T.Toffoli, Conservative logic, International Journal of Theoretical Physics, 21: , [8] Maslow and Miller, Comparison of the cost metrics through investigation of the relation between optimal NCV and optimal NCT three-qubit reversible circuits,iet,2007. Figure9.3. Layout of 16bit reversible ALU VII CONCLUSION In this paper the design and synthesis of 16bit ALU using reversible logic gates instead of irreversible gates. The performance checks of various modules are carried out by using Xilinx and GPDK 180nm technology Cadence tools and also compared parameter difference between the reversible and irreversible ALU. This work shows the efficiency of reversible logic in terms of power reduction as there is 0.252μw and 0.781μw power reduction in 4 bit and 16 bit reversible logic based Arithmetic and logic unit respectively when compared with 4 bit and 16 bit Irreversible logic based arithmetic and logic unit. VIII REFERENCES [1] R.Landauer, Irreversibility and Heat Generation in the Computational Process, IBM Journal of Research and Development, 5,pp ,1961.