PIPELINED DIVISION OF SIGNED NUMBERS WITH THE USE OF RESIDUE ARITHMETIC FOR SMALL NUMBER RANGE WITH THE PROGRAMMABLE GATE ARRAY

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1 POZNAN UNIVE RSITY OF TE CHNOLOGY ACADE MIC JOURNALS No 76 Electrical Engineering 03 Robert SMYK* Zenon ULMAN* Maciej CZYŻAK* PIPELINED DIVISION OF SIGNED NUMBERS WITH THE USE OF RESIDUE ARITHMETIC FOR SMALL NUMBER RANGE WITH THE PROGRAMMABLE GATE ARRAY In thi wor an architecture of the pipelined igned reidue divider for the mall number range i preented. It operation i baed on reciprocal calculation and multiplication by the dividend. The divior in the igned binary form i ued to compute the approximated reciprocal in the reidue form by the table loo-up. In order to limit the loo-up table addre an algoritm baed on egmentation of the divior into two egment i ued. The approximate reciprocal tranformed to reidue repreentation with the proper ign i tored in loo-up table. During operation it i multiplied by the dividend in the reidue form and ubequently caled. The pipelined realization of the divider in the FPGA environment i alo hown.. INTRODUCTION In the digital ignal proceing the diviion i uually performed when the quotient of two ignal ha to be determined, for example, in computation of the phae hift before arctangent calculation. The reidue arithmetic [,, 3] i a tool that can be ued for realization of DSP algorithm due to it decompoitional propertie with repect to addition, ubtraction and epecially to multiplication becaue multiplication in one large integer ring can be replaced by a et of multiplication performed in mall integer ring in parallel. The other important feature i the poibility to decompoe the complex multiplication of Gauian number in imilar manner a that for integer uing derivative ytem uch a the MQRNS (Modified Quadratic Reidue Number Sytem) [4]. However, other operation in reidue arithmetic uch a revere converion, ign detection, magnitude comparion, caling and diviion are difficult. The diviion of reidue number can be carried out by converting them to a weighted ytem, performing diviion and converting bac to the reidue form. However, diviion of reidue number partly or fully in reidue arithmetic can be more effective. The algorithm * Gdań Univerity of Technology.

2 8 Robert Smy, Zenon Ulman, Maciej Czyża of reidue diviion belong mainly to a group of ubtractive [5, 6, 7] or multiplicative [8, 9, 0] algorithm. The multiplicative algorithm compute, uing the Mixed-Radix Converion (MRC) [], the reciprocal of the divior which i ubequently multiplied by the dividend. Alo two algorithm were preented [, ], where the MRC, ign detection, overflow detection are not needed but in the former the converion of the divior and dividend to the binary ytem i neceary. They have better time-hardware complexity, however, they are iterative what mae them not uitable for pipelined proceing. The algorithm baed on iterative reciprocal computation wa given in [3]. In thi wor an architecture of the pipelined reidue divider of igned number i hown. The implementation ue a non-iterative reidue multiplicative diviion algorithm. The approximate reciprocal of the divior i computed by the loo-up with the ue of the algorithm from [4] baed on egmentation of the divior in the binary form in two egment that addre the loo-up table. In thi way the ize of loo-up table i reduced. The algorithm ha fixed diviion time. It i aumed that the architecture will ue 6-bit loo-up table available in the ilinx FPGA. The algorithm permit to implement the diviion for igned -bit number with the imum diviion error maller than.. THE RESIDUE NUMBER SYSTEM(RNS) The RNS with the bae B { m m,.., } moduli and the number range integer N from [, -] =, m p, where m j, j=,,..,p, are named M = p m j j=, allow to repreent the nonnegative 0 M by the digit vector ( N N,..., N ) ( n, n..., n ), m m m p =, where N m j i the leat nonnegative reidue from diviion of N by m j, j =,,3,..., p. Thi repreentation i one-to-one correpondence if the moduli are pairwie relatively prime. In uch a cae there i a unique mapping given by the Chinee Remainder Theorem [-]. The main advantage of the RNS i due to the fact that addition, ubtraction and multiplication of two RNS number can be performed independently on the correponding pair of reidue. For the number with the ign denoted a, if M i even, = N for N < M /, and = N M, if N M /. If M i odd, = N for N < ( M ) /, and = N M, if N ( M ) /. A the multiplication of igned number i ued in the method of diviion preented below, we hall illutrate it with an example. p

3 Pipelined diviion of igned number with the ue of reidue 9 Example. Multiplication of igned number in reidue arithmetic. Let B={3,3,9,7,5,3), we have M= and let z = 35 {3, 4, 6, 8,0,} z = 70 M 70= {6, 3,7,, 5, } We want to obtain the product P= z z.by performing the multiplication in the individual ring we obtain the reidue of P P= 3 6, 4 3, 6 7, 8, 0 5, = 4,30,5,7,0, ( ) ( ) Thee reidue are the reidue of the number M-450= , that repreent the product P in the M ring. 3. DIVISION ALGORITHM In the reidue diviion algorithm we have to find an integer Q ~ approximate Q = / Y with the imum acceptable diviion error, ε div. The reciprocal of the divior ha to be determined with uch accuracy that after multiplication by dividend, the reulting diviion error i maller than the aumed imum acceptable error. The additional requirement impoed on the algorithm may be the ue of mall table for the reciprocal computation. In the algorithm initially m-bit divior ( m ) i decompoed into m- bit egment and -bit egment with not exceeding 7 bit. For computation of the divior by looup uch egmentation allow to ue maller loo-up table than in the cae when the loo-up table i addreed with the full repreentation of the divior. The reciprocal R can be decompoed into two part in the following manner b R= = =. () Y a+ b a a b) The tranformation of () into the form that allow to ue mall loo-up table wa preented in [4] along the reciprocal computation algorithm. In the following a hort review i provided. It i een that the computation of /( a b)) require m-bit addre, in order to replace it with log a -bit addre we may try to replace b by a uitably choen contant, K that lead to b b, () a b) a K ) and in effect we obtain the following reciprocal approximation ~ b R =, (3) a a 5 3 that

4 0 Robert Smy, Zenon Ulman, Maciej Czyża where a Y / = and = Y. We ee that /a can be computed by the loo-up b uing m- bit. For a> 0 we replace b by K that approximate b in [ 0, ]. Remar that for a=0, /b can be looed up uing -bit. The reciprocal approximation error reulting from uing K intead of b i expreed a [4] ~ b ( K b) R R = ε ( a, b, =. (4) a b) A K ha to approximate b, it hould belong to 0, b ], where b = i [ the end of the interval. It i evident that ε(a, b, i imal with repect to a when a = and with repect to b when b = b or for certain b= b. Uing (4) and a = a min, the imum diviion error for the imum dividend, can be written a ε = ε (,b,k ) div. (5) The extreme of (4) with repect to b i obtained a Uing thi b b = a+ a K ) (6), we want to equalize the diviion error, for b and b ε a b, K = ε a, b, K (7) ( ) ( ) min, min (7) uing (4) can be written in the following form b ( b b ( b = (8) a+ b a+ b Inerting (6) into (8), we obtain the equation for K that allow to determine K that provide the fulfilment of (8) b 4 b b 4 b b b ( + + ) K + ( + 4 b ) K 4 b 4 + = 0 (9) Sample olution of (9) are given in Example. Example. Aume the length of the divior Y equal to m= bit and the length of a and b equal to 6 bit. We have a = min 64 and b = 63. The coefficient of the quadratic equation (9) are A = 8. 8, B = 3. 84, C = Moreover, we have b =. 05 and the optimum K = In effect we obtain for = and for b, the imum diviion error equal to ε ( K, b ) = 3.9 and for b to ε ( K, b ) = 3. 9.

5 Pipelined diviion of igned number with the ue of reidue In order to reduce thi error we may increae the length of a to 7 bit and horten b to 5 bit. We then have a = min 8 and b = 3. The coefficient of (9) are A =., B = 3. 74, C = , and the optimum K = 5. and b =.03. In effect we have for, ε ( K, b ) = and ε ( K, b ) = HARDWARE REALIZATION Now we hall conider the realization of the divider with the ue of reidue arithmetic. Such realization require the tranformation of the approximated reciprocal value to integer. Thi tranformation i done by the multiplication by a contant K and rounding off the reult. After tranforming of (3) to integer we get K K b K (0) Y a a ( a+ where {} denote rounding off to nearet integer. K in (0) hould give the appropriate dynamic number range to repreent the both term and provide for the allowable error value that arie after multiplication of the round-off error of the econd term by b. The imum value of thi error hould not caue the unacceptable diviion error. The upper bound of thi error i reached for b and and imal value of a, a c for which the compenation of the reciprocal approximation error i till needed. It i eay to verify that for the conidered 8 number range of diviion of, we have a c =. The error of the econd term of (0) ha to fulfill the following condition b K K < K a c a c K a c a c K 0. + ( + ) 5. () ( ) Repreenting the econd term in () a ( a ) + ε r where ε r i the rounding error, we obtain the bound on ε r to limit the error of tranformation to integer to K εr <, () b moreover, K ha to fulfill the condition K > a ( a, (3) c c +

6 Robert Smy, Zenon Ulman, Maciej Czyża For example, for a 56 we have K > , that give after c = inerting into () ε < 0. r 307. We may avoid the round-off error, by aumming K a the multiple of the a min ( a min + = , for example, , that lighly extend the error bound. However, there can be additional requirement impoed on K, becaue certain value may facilitate the deign of the caling circuit that perform caling after diviion. Example 3. Realization of diviion for three divior value 7, 9 and 39 with a=64, 8, 56, repectively, and imum of b=63, for which the highet level of error compenation i needed and the error due to round-off of the econd term in (0) may reach it imum. Firt we hall we conider Y = 7. We have a=64 and b=63. a = 64 ( ) = , and we will adopt K = 597. Such choice of K = reult from the requirement of caling after diviion, caling become more imple when the caling factor i a product of the moduli of the RNS bae. Uing (0) we get K = 63 = { 495.5} 63 {.07} = 0 Y We obtain the approximate quotient a ~ Q = K / K = = { 8.46} = 8 Y 597 wherea Q = = Y In the econd cae we hall conider a in the middle of it interval. Y = 93. We have a=8 and b=63. Here a = 8 ( ) = We get K = 63 = Y We obtain the approximate quotient a ~ Q = K / K = = Y 597 { 47.5} 63 { 7.04} = 807 { 0.69} =

7 Pipelined diviion of igned number with the ue of reidue 3 wherea Q = =. 39. Y Finally we conider the diviion for Y = 3 39, where a=56, that mean that it reache the end point of interval in which the reciprocal approximation error i compenated. We have a=56 and b=63. Here a = 56 ( ) = K = 63 = Y We obtain the approximate quotient a ~ Q = K / K = = Y3 597 wherea Q = =. 83. Y { 63.87} 63 {.04} = 498 {.76} 3 3 = 3 We can etimate the required number range by (4). K M= K b (4) a c ( a c+ In our cae we have a = min 64, b = 63, K = 597 and K = The dynamic range of the firt term in (4) i equal to and of the econd term 44. Finally we may etimate the require dynamic range a M D = log ( = log = 4 bit. We ee that after caling the binary ize of quotient obtained from thi reidue channel will not exceed 7 bit. The RNS bae ha been choen a B = { 3, 3, 9, 3,} with M= and, given above, K = = 597. For the RNS architecture we aume that , and ha the x,x,x,x,, where x =, j=,,...,5. and reidue repreentation ( ) 3 4 x5 Y i repreented in -bit igned binary form. Q ~ K K b = K m m a a (a m + In Fig. an architecture that implement (5) i depicted. j mm m m j (5)

8 4 Robert Smy, Zenon Ulman, Maciej Czyża Fig.. The architecture of the reidue divider The dividend i repreented at the input a (,..., ). The, m m m caling converter cale Y to the range [, ] and output -bit binary word where the mot ignificant bit i the ign bit, the next 5 bit form operand a and ix leat ignificant bit repreent operand b. For each reidue channel the ame configuration of component are ued. ROM mod mod m i compute K a m i and ROM3 mod m i compute a m i compute m i 6, ROM b,. In the m i next tage the multiplication i performed (MULT mod m i ) and in the following tage the ubtraction i performed (BA mod m ). In the final tage the obtained reidue are caled by K b m i K. If a=0 the ROM4 i mod mi are applied that compute and ROM5 detect the ign. The output of thee circuit are multiplexed with thee obtained from (5). In thi implified divider architecture there i no divior zero detection.

9 Pipelined diviion of igned number with the ue of reidue 5 The architecture ha been implemented in the ilinx environment uing the device from the Virtex-6 family. Below the ynthei report i hown. The pipelining rate of.74 n ha been attained. It i poible to obtain.5 n that correpond to MHz. The pipelining rate i greater becaue of reduction of the number of pipeline tage. Selected Device : 6vcx40tff784- Slice Logic Utilization: Number of lice regiter: 443 out of Number of lice LUT: 908 out of 5070 Number ued a logic: 834 out of 5070 Number ued a memory: 74 out of Number ued a SRL: 74 Timing Summary: Minimum period:.747 n (imum frequency: MHz) Minimum input arrival time before cloc: 0.550n Maximum output required time after cloc: 0.659n 5. CONCLUSIONS The paper preent the implementation of the pipelined reidue divider for - bit number range in the ilinx FPGA environment. The divider mae ue of the multiplicative diviion algorithm with the two-term reciprocal approximation. The reidue error belong to [ 3.9,3.9], however for two' complement coding the error i halved. The divider architecture ue 5-bit moduli o that eay implementation i poible a in thi environment 6-bit LUT are available. The architecture ue neither large memorie nor multiplier. REFERENCES [] Szabo N.S., Tanaa R.I.: Reidue Arithmetic and it Application to Computer Technology, McGraw-Hill, New Yor, 967. [] Sodertrand M. et al., Reidue Number Sytem Arithmetic, Modern Application in Digital Signal Proceing, IEEE Pre, NY, 986. [3] Omondi A., Premumar B., Reidue Number Sytem: Theory and Implementation, London, Imperial College Pre, 007. [4] Jenin W.K., Krogmeier J.V.: The deign of dual-mode complex ignal proceor baed on quadratic modular number code, IEEE Tran.on Circuit and Sytem, Volume 34, Number 4, pp , 987.

10 6 Robert Smy, Zenon Ulman, Maciej Czyża [5] Keir, Y.A, Cheney P.W., Tanenbaum M.: Diviion and overflow detection in reidue number ytem, IRE Tran. Electron. Comput., Volume EC-, pp , 96. [6] Kinohita E., Koao H., Koyima Y.: General diviion in ymmetric reidue number ytem, IEEE Tran. on Computer, Volume C-, pp.34-4, 973. [7] Banerji D.K., Cheung T.Y., Ganean V.: A high peed diviion method in reidue arithmetic, Proc. of 5th IEEE Symp.on Comput. Arithm., pp , 98. [8] Lin, M. L., Lei, E., McInni B.: Diviion and ign detection algorithm for reidue number ytem, Comput. Math. Appl. Volume 0, Number4/5, pp , 984. [9] Chren W.A., Jr.: A new reidue number ytem diviion algorithm, Comput. Math. Appl., vol.9, Number 7, pp.3-9, 990. [0] Lu M, Chiang Jen-Shiun: A novel diviion algorithm for the reidue number ytem, IEEE Tran. on Comput., Volume C-4, pp.06-03, 99. [] Hiaat A.A., Zohdy,H.A.A.: Semi-cutom VLSI deign and implementation of a new efficient RNS diviion algorithm, Computer Journal, Volume 4, Number3, pp.3-40, 999. [] Talameh S., Siy P.: Arithmetic diviion in RNS uing Galoi field GF(p), Comput. Math. Appl., Volume 39, pp. 7-38, 000. [3] Hitz, M.A., Kaltofen, E: Integer diviion in reidue number ytem, IEEE Tran. on Computer, Volume C-44, pp , 995. [4] Czyza, M.: Noniterative mall range reidue diviion, RADIOELEKTRONIKA 00, May 4-6, Bratilava, pp.-4, 00.