12/31/2010. Overview. 10-Combinational Circuit Design Text: Unit 8. Limited Fan-in. Limited Fan-in. Limited Fan-in. Limited Fan-in

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1 Overview 10-ombinational ircuit esign Text: Unit 8 Gates with elays and Timing Other Hazards GR/ISS 201 igital Operations and omputations Winter 2011 r. Louie 2 Practical logic gates are limited by the number of inputs they can handle (fan-in) Similar constraints on the number of gates the output can be connected to (fan-out) Solution to limited fan-in: factor into a multi-level expression Solution to limited fan-out: use buffers (discussed in the next lecture) onsider (,,, ) = m(0, 3, 4, 5, 8, 9, 10, 14, 15) esign using NOR gates r. Louie 3 r. Louie 4 Recall NOR-NOR requires starting with PoS form = = =( ) =(+++)( ++ +)( + +)(+ + ) (+ +) Next = {() } ={(+++) +( ++ +) +( + +) +(+ + ) +(+ +) } r. Louie 5 r. Louie 6 1

2 ={(+++) +( ++ +) +( + +) +( + + ) +(+ +) } This requires: Three, 3-input NOR Two, 4-input NOR One, 5-input NOR What if we are limited to 3-input NORs only? Start with: = actor to: = ( + ) + (+) + onvert this to NOR-NOR form r. Louie 7 r. Louie 8 = ( + ) + (+) + = [+ +(+)( + )][+ + ][ + +] Next = {() } = [+ +(+)( + )][+ + ][ + +] Next = {() } = {([+ +(+)( + )][+ + ][ + +]) } = {[++(+)( + )] +[+ + ] +[ + +] } Using (+)( + ) = {[(+)( + )] } and = [( ) ] yields: = {[++((+) +( + ) ) ] +[+ +(+) ] +[ + +] } r. Louie 9 r. Louie 10 uild the circuit of = {[++((+) +( + ) ) ] +[+ +( +) ] +[ + +] } = ( + ) + (+) + Recall that you can build: = [+ +(+)( + )][+ + ][ + +] r. Louie 11 r. Louie 12 2

3 = [+ +(+)( + )][+ + ][ + +] nd replace the gates with NORs, and invert the single literal inputs to levels 1, 3, 5 etc (see text page 188) esign procedure for multi-output circuits Minimize individually (common terms are usually lost when factoring) actor individually as needed to meet fan-in requirements r. Louie 13 r. Louie 14 Gate elays Output changes do not occur instantaneously Propagation delay, On the order of 1 nanosecond Propagation delay is not symmetric 0 to to 0 2 In multi-level circuits, the delay can be important Gate elays of an inverter propagation delay X X time r. Louie 15 r. Louie 16 ssume the delays are 20 ns for each gate Let = 1 and =0, changes as shown 20 ns 20 ns raw the timing diagram if the delay for gate 1 is 10 ns and gate 2 is 15 ns ssume is low from 0 to 10ns and high from 10 ns to 30 ns = 0, and = 1 time 20 ns r. Louie 17 r. Louie 18 3

4 Hazards in ombinational Logic raw the timing diagram if the delay for gate 1 is 10 ns and gate 2 is 15 ns Transients can occur if propagation delays are different for the various I Static 1-hazard: when the output should be a 1 but it momentarily goes to 0 in response to an input change Static 0-hazard: when the output should be a 0 but it momentarily goes to 1 in response to an input change time (ns) r. Louie 19 r. Louie 20 Hazards in ombinational Logic ynamic hazard: when the output is supposed to change from 1 to 0 or 0 to 1 and the change occurs three or more times Hazards in ombinational Logic onsider: = + ssume that =1 =1 Then: = + = 1 should remain at 1 when changes from 0 to 1 or 1 to 0 time r. Louie 21 r. Louie 22 Hazards in ombinational Logic Timing diagram: Hazards in ombinational Logic Is this a static 1 or static 0 hazard? Static 1 hazard time (ns) time (ns) r. Louie 23 r. Louie 24 4

5 Hazards in ombinational Logic Hazards in ombinational Logic We can identify potential hazards by examining K-maps No single loop covers and If ==1 and changes, both can momentarily go to Procedure for examining K-maps for hazards Write down SoP form of expression Plot each term on the K-map and loop as necessary If any two adjacent 1s are not covered by the same loop, a static 1 hazard exists for the transition between the two 1s or an n-variable k-map, the transition occurs when one variable changes and the other n-1 variables are held constant r. Louie 25 r. Louie 26 Hazards in ombinational Logic To remove the hazard Hazards in ombinational Logic ircuit with the hazard removed r. Louie 27 r. Louie 28 Hazards in ombinational Logic Static 0-hazards occur analogously with 0s on the K-map Procedure for the removal of the hazard is analogous to removal of static 1-hazards Hazards in ombinational Logic esign of circuits without static hazards: 1. ind a SoP expression of in which every pair of adjacent 1s is covered by a 1-term This can be done by summing all the prime implicants two-level N-OR circuit will be free of 1- and 0- static hazards and dynamic hazards 2. If a different form of is needed, algebraically manipulate, but treat literals and their complements as independent variables r. Louie 29 r. Louie 30 5

6 erive an expression for that eliminates static 0-hazards erive an expression for that eliminates static 0-hazards = (+)( +)( + +)(+)(+ +)( + + ) r. Louie 31 r. Louie 32 6