Advanced Digital Logic Design EECS 303. Multi-level example. Two-level form. Multi-level form A B C. Multi-level logic

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1 dvanced igital Logic esign S 33 Multi-level example Teacher: Robert ick Office: L477 Tech mail: dickrp@northwestern.edu Phone: So far, we have talked about two-level logic ewest number of levels that is fully general However, there are some circuits that can more efficiently be implemented using three or more levels ven basic functions, like NNS and NORS, are commonly composed of multiple gates if the fan-in is high 4 Robert ick dvanced igital Logic esign Two-level form Two-level form X(,,,,,, G) = G x 5 6 G 5 Robert ick dvanced igital Logic esign x 5 6 G 6 x 3-input N gates x 7-input OR gate (may not exist!) 25 wires (9 literals plus 6 internal wires) 6 Robert ick dvanced igital Logic esign Multi-level form Multi-level form actor: G X(,,,,,,G) = G = ( + + )( + ) + G 4 x G 2 3 x 3-input OR gate, 2 x 2-input OR gates x 3-input N gate wires (7 literals plus 3 internal wires) 4 x 7 Robert ick dvanced igital Logic esign 8 Robert ick dvanced igital Logic esign Multi-level implementation of NN8 Multi-level logic = ( + ) + Level Level 2 Level 3 Level 4 Orig inal N OR Netwo rk \ G Introduction and ons ervation of ubbles \ G onvert middle Ns to NORs with inverted inputs Redrawn in terms of conventional NN Gates \ \ G 9 Robert ick dvanced igital Logic esign Robert ick dvanced igital Logic esign

2 Multi-level logic NN/NOR conversion for uneven paths Level Level 2 Level 3 Level 4 \ G Same beginning netwo rk after introduction of bubbles X Orig inal circuit X X dd double bubbles at inputs \ \ \ \ G inal netwo rk, redrawn in NOR only fo rm \X \ \ is tribute bubbles s ome mis matches \X Ins ert inverters to fix mis matches Robert ick dvanced igital Logic esign 2 Robert ick dvanced igital Logic esign Multi-level minimization objectives Multi-level minimization actor out common sub-logic (reduce fan-in, increase gate levels), subject to timing constraints Map factored form onto library of gates Minimize number of literals (correlates with number of wires) X = ( + )( + ( + )) + ( + )(G) an interactively apply the following operations ecomposition xtraction actoring Substitution ollapsing 4 Robert ick dvanced igital Logic esign 5 Robert ick dvanced igital Logic esign Multi-level minimization ecomposition Recall that two-level minimization is difficult Quine-Mcluskey is too slow for large problems Resort to potentially sub-optimal heuristic spresso Multi-level minimization is much harder No known efficient algorithm gives optimal solution MIS uses heuristics to usually produce good solutions Take a single oolean expression and replace it with a collection of new expressions L rewritten as L = L = MN + M N M = N = + 2 literals 8 literals 6 Robert ick dvanced igital Logic esign 7 Robert ick dvanced igital Logic esign ecomposition ecomposition L = = ( + ) + ( + ) = ( + ) + ()( + ) M = N = + L = MN + M N efo re ecompos ition fter ecompos ition 8 Robert ick dvanced igital Logic esign 9 Robert ick dvanced igital Logic esign

3 xtraction xtraction xtraction is decomposition applied to multiple functions The best decomposition for a single function may not be the best if there are multiple outputs Ideally, extracted sub-function can be re-used in producing many outputs L = ( + ) + M = ( + ) N = an be re-written as L = XY + M = X N = Y X = + Y = literals literals 2 Robert ick dvanced igital Logic esign 2 Robert ick dvanced igital Logic esign xtraction xtraction example X L Y M N efo re xtraction fter xtraction Gate count has improved, literals is unchanged L M N Given equations of a oolean Network L = + + G + G literals M = N = + ind the best kernel of these functions. If the kernel is ( + ), then L = M + P + G + G 22 literals M = P + P N = + P = + 22 Robert ick dvanced igital Logic esign 23 Robert ick dvanced igital Logic esign ube extraction actoring an restrict divisors to single cubes L = + + G 6 literals M = G N = + We can obtain the best cube to divide the functions L = P + P + G 5 literals M = PG N = + P = xpression in two-level form re-expressed in multi-level form without introducing intermediate functions an be rewritten as L = L = ( + )( + ) + 9 literals 5 literals 24 Robert ick dvanced igital Logic esign 25 Robert ick dvanced igital Logic esign actoring Substitution xpress L in terms of M L = + M = + L rewritten in terms of M L = M( + ) M = + 5 literals 5 literals efo re acto ring fter actoring 26 Robert ick dvanced igital Logic esign 27 Robert ick dvanced igital Logic esign

4 ollapsing Redundancy Reverse of substitution. Sometimes eliminates levels to meet timing constraints. L = M( + ) M = + L = ( + )( + ) = = + 5 literals only 2 additional Minimizing gate count and literals isn t always good for performance or power consumption Using redundant sub-circuits can result in improvements The wiring required to re-use sub-functions can result in larger delays than redundant sub-functions 28 Robert ick dvanced igital Logic esign 29 Robert ick dvanced igital Logic esign oolean division oolean division L = PQ + R P divisor Q quotient R remainder X = Y = + X divided by Y expressed as X = Y ( + ) + P and Q are symmetrical inding divisors that lead greatest number of common subexpressions is difficult L = + + M = + M does not divide L under algebraic division rules M does divide L under oolean rules (very large number of these!) L/M = ( + ) 3 Robert ick dvanced igital Logic esign 3 Robert ick dvanced igital Logic esign oolean division oolean division L = + + M = + L = ( + )( + ) + = ( + )( + ) + This follows from writing L in MQ + R form L = M(( + )) + = ( + )( + ) + = ( ) + = ( + ) + = Robert ick dvanced igital Logic esign 33 Robert ick dvanced igital Logic esign Multi-level minimization definitions Multi-level minimization definitions variable is a symbol representing a single coordinate in a oolean space, e.g., or Literal is a variable or its negation, e.g., or cube,, is a set of literals, e.g., or onsider a sum-of-products expression L = + + G + G The primary divisors of an expression form a set of expressions (L) = {L/ is a cube} quation is cube-free if no cubes divide it evenly + is cube-free + is not cube-free ivided evenly by 35 Robert ick dvanced igital Logic esign 36 Robert ick dvanced igital Logic esign

5 Multi-level minimization definitions Kernel The kernels of an expression are sets of expressions K(L) = {G G (L) and G is cube-free} In other words, the kernels are divisors of the function for cube quotients that can not be evenly divided (remainder-free) by other cubes The cube used to divide L to obtain the kernel K(L) is called the co-kernel L = + + G + G ube Primary divisor Kernel (cube free) ( + G + ) k ( + ) k 2 (G + ) k 3 ( + + ) no ( + + ) no ( + ) k 4 G ( + ) k 5 ( + + ) k 6 37 Robert ick dvanced igital Logic esign 38 Robert ick dvanced igital Logic esign ivisor selection ivisor selection Kernels are often good divisors, extract and substitute L = + + G + G ivide by k 6 = ( + + ) 7 literals L = k 4 + G + G + k 6 Remaining kernel: k 5 = ( + ) L = + + G + G + k 6 Remaining kernels: k = ( + G),k 4 = ( + ),k 5 = ( + ) Pick one L = k 4 + G + G + k 6 L = k 4 + G + G + k 6 L = k 4 + Gk 5 + k 6 nd result L = ( + ) + G( + ) + ( + + ) literals 39 Robert ick dvanced igital Logic esign 4 Robert ick dvanced igital Logic esign Node simplification Node simplification uring multi-level logic synthesis, representation broken into sub-functions ach sub-function (e.g., SOP form) needs to be minimized L = + + G + G Similar to using Karnaugh Maps, Quine Mcluskey, or spresso to simply expressions L = + + = + (,,) 4 Robert ick dvanced igital Logic esign 42 Robert ick dvanced igital Logic esign Node simplification Recall that two-level simplification can be improved using on t are information Need to find on t are automatically from oolean network Take advantage of satisfiability on t ares Input can never occur Take advantage of observability on t ares Output is ignored for certain inputs Ideal Real Inertial Transport time 43 Robert ick dvanced igital Logic esign 46 Robert ick dvanced igital Logic esign

6 Ideal No delay, outputs respond instantly to inputs Transport Output shifted by some fixed duration ll input changes reflected at output Inertial Transitions that are not stable for more than some threshold period of time are absorbed by the gate Provides a coarse approximation to real digital logic gate behavior Real Outputs quickly respond to input changes However, output changes have limited slew-rates 47 Robert ick dvanced igital Logic esign 48 Robert ick dvanced igital Logic esign R delay IO thresholds What happens when a transistor drives another transistor? Recall how MOS transistors work 49 Robert ick dvanced igital Logic esign 5 Robert ick dvanced igital Logic esign IO thresholds Molten transistor V igital is a simplifying concept in a (macroscopically) analog world To treat signals as digital, need to define a dividing line between false and true What actually happens to the next stage when the voltage is at that line? NMOS V GS > V T PMOS V GS < V T =? = =? = = = V SS 52 Robert ick dvanced igital Logic esign 53 Robert ick dvanced igital Logic esign IO thresholds IO thresholds efine valid ranges of logic high and logic low signals Undefined signals considered invalid etter However, still have a problem What happens if the output of a gate is near that threshold? Slight variation between gates might result in crossing this threshold for next gate How to compensate? Use separate input and output thresholds 54 Robert ick dvanced igital Logic esign 55 Robert ick dvanced igital Logic esign

7 Separate IO thresholds Schmitt triggers Now, we can safely treat the system as digital However, digital systems talk with analog systems It is necessary to deal with noisy signals Real slew isn t ideal transition 56 Robert ick dvanced igital Logic esign 57 Robert ick dvanced igital Logic esign Reason for gradual transition MOS NOT is R network V V logic stage is an R network Whenever a transition occurs, capacitance is driven through resistance onsider the implementation of a MOS inverter V SS V SS 58 Robert ick dvanced igital Logic esign 59 Robert ick dvanced igital Logic esign What is driven in NN2? ebouncing Mechanical switches bounce! What happens if multiple pulses? Mutliple state transitions Need to clean up signal 6 Robert ick dvanced igital Logic esign 6 Robert ick dvanced igital Logic esign ebouncing Improving device delay 5 V Schmidt trig. R ecrease driven resistance and load Use smaller transistors Use shorter wire Use wider wire (can increase load) -.e-3-5.e-4.e+ 5.e-4.e-3.5e-3 T (s) 62 Robert ick dvanced igital Logic esign 63 Robert ick dvanced igital Logic esign

8 Improving device delay riving large loads Increase drive by increasing width of driving transistors auses problems Larger transistors provide larger loads to their inputs In general, keep transistors small unless they absolutely need to drive large loads Sometimes large loads need to be driven Long wires Output pads What happens if we go from a minimum-size inverter to a huge inverter? Huge delay driving huge inverter s gate 64 Robert ick dvanced igital Logic esign 65 Robert ick dvanced igital Logic esign Tapered buffer chain Useful delay: ebouncing Instead, gradually increase buffers in chain Optimal number of stages: ln ( IG/SMLL) Stage width exponentially increases in α W = W MIN α W 2 = W MIN α W 3 = W MIN α 2 Mechanical switches bounce Noisy transition Use R delay network to decrease transition speed onvert multiple noisy to single smooth transition Use Schmitt trigger to clean signal 66 Robert ick dvanced igital Logic esign 67 Robert ick dvanced igital Logic esign elay estimation in multi-level circuits Topological sort an get delay for a gate by knowing its drive (resistance) and the load it drives (R) Gate libraries will have this information Still need to get network delay onduct topological sort of network to find earliest start times (ST) lways visit a node s parent before visiting it ST is maximum any parent s ST plus it s delay 5 ST = max(9, ) Robert ick dvanced igital Logic esign 69 Robert ick dvanced igital Logic esign Slack Useful delay: Rising edge pulse shaping an use reverse topological sort from end nodes (given some target delay) to get latest start time (LST) Subtract delays and take minimum over children instead of adding delays and taking maximum over parents Subtract ST from LST to get node slack Gates with lowest slack are on critical path Make this path faster......or save area (at the expense of speed) on non-critical paths Problem: Pulse width poorly controlled 7 Robert ick dvanced igital Logic esign 7 Robert ick dvanced igital Logic esign

9 Useful delay: Pulse rising/falling edge pulse shaping ynamic hazards losed switch xxxxx Initially undefined xxxx Resistor Open Switch + Open switch Potential for two or more spurious transitions before intended transition Results from uneven path delays in some multi-level circuits ynamic hazards Problem: Pulse width poorly controlled 72 Robert ick dvanced igital Logic esign 74 Robert ick dvanced igital Logic esign ynamic hazards liminating dynamic hazards G S low Very slow Some approaches allow preservation of multi-level structure Quite complicated to apply Simpler solution onvert to two-level implementation 75 Robert ick dvanced igital Logic esign 76 Robert ick dvanced igital Logic esign Static hazards Problems with glitches Still have static hazards Potential for transient change of output to incorrect value Static hazard Static hazard These transitions result in incorrect output values at some times lso result in uselessly charging and discharging wire and gate capacitances through wire, gate, and channel resistances Increase power consumption 77 Robert ick dvanced igital Logic esign 78 Robert ick dvanced igital Logic esign Glitches increase power consumption etecting hazards V V The observable effect of a hazard is a glitch circuit that might exhibit a glitch has a hazard V SS V SS Whether or not a hazard is observed as a glitch depends on relative gate delays Relative gate delays change depending on a number of factors onditions during fabrication, temperature, age, etc. est to use abstract reasoning to determine whether hazards might be observed in practice, under some conditions 79 Robert ick dvanced igital Logic esign 8 Robert ick dvanced igital Logic esign

10 liminating static hazards liminating static hazards G G = = input change within product term G = = ( is s till ) G = + G = ( is ) 8 Robert ick dvanced igital Logic esign 82 Robert ick dvanced igital Logic esign liminating static hazards Where do static hazards really come from? dd redundant primes covering all - transitions in SOP dd redundant primes covering all - transitions in POS learly primes can be used, consider contradiction stemming from assumption that non-prime is necessary to cover a transition Static-: Static-: + ssume SOP form has no product terms containing a variable in complemented and uncomplemented forms Reasonable assumption, if true, drop product term 83 Robert ick dvanced igital Logic esign 84 Robert ick dvanced igital Logic esign Where do static hazards really come from? Living with hazards ssume POS form has no sum terms containing a variable in complemented and uncomplemented forms Reasonable assumption, if true, drop sum term ssume only one input switches at a time onclusion: SOP has no -hazards and POS has no -hazards In other words, if you are doing two-level design, you need not analyze the other form for hazards Sometimes hazards can be tolerated ombinational logic whose outputs aren t observed at all times Synchronous systems Systems without tight power consumption limits 85 Robert ick dvanced igital Logic esign 86 Robert ick dvanced igital Logic esign Summary rief review of cascaded carry lookahead adder ommon LU operations Overview of memory types behavior 87 Robert ick dvanced igital Logic esign