Problem Set 4 Solutions

Transcription

1 SE 26 igital omputers: Organization and Logical esign Jon Turner Problem Set 4 Solutions 1. Find a minimal logic expression for the NN/NOR circuit shown below. The circuit implements the expression ((() + ) + ) = (( + + ) + ) = (+ ) = (+ ) = ( + ) = + 2. Give an equivalent N/OR circuit, corresponding to the NN/NOR circuit shown below. The circuit at left below was obtained by re-drawing the NOR gates in the alternate form. The circuit at right was obtained by cancelling redundant inversions and replacing others with inverters

2 This makes it obvious that the function implemented by this circuit is ( ), allowing us to simplify the circuit further to the one shown below. 3. How many transistors are used by original circuit in the previous problem? How many are used by the circuit in your solution? The original circuit had four NNs and NORs, plus an inverter, giving 18 transistors. The first of the two solution circuits has four N/OR gates, plus two inverters, giving 28 transistors. The final solution has Find a less-expensive NN/NOR equivalent for the circuit below. ompare the number of transistors used by the two circuits. The NN/NOR circuit appears at right. This circuit has =22 transistors, vs =28 transistors for the original circuit

3 5. The and function is associative. That is ( and ) and = and ( and ). What about the nand function? Justify your answer. ased on your answer, show would you implement a nand function with 8 inputs, using just simple NN and NOR gates (that is, gates with 2 inputs) and inverters. If a NN or NOR gate has a delay of 2 and an inverter has a delay of 1, what is the worst-case propagation delay for your gate implementation? ompare the delay for your circuit to the delay for an eight input NN gate implemented directly in MOS transistors (generalize the NN3 on page 4.11 of the notes). lso, compare the transistor counts for the two circuits. The nand function is not associative, since ( nand ) nand = (() ) = +, while nand ( nand ) = (() ) = + and these are clearly not equal. The figure below shows one way to implement an eight input nand function with simple NN and NOR gates. This circuit has NOR gates in the center stage and has a delay of 6 ns. If we were to implement the NN function directly, using an eight input gate, the delay would be 8 ns (since there are eight pull-downs in series, making the falling transition four times slower than the 2 input gate). The transistor counts for the two circuits are 28 and 16 respectively, so the direct implementation is uses significantly fewer transistors at the cost of a relatively small increase in delay

4 6. Find a circuit using the minimum number of 4 input LUTs that implements the three logic equations shown below. = ( + F )( + E) Y = ( + E ) + ( + + F) = ( + E)( + F) If we let U = ( + E) = ( + E ) = ( + E), we can re-write the above expressions as = ( + F )U Y = U + ( + + F) = U( + F) Note that each of these expressions involves just four variables,,, F and U. So, we can use one LUT to implement U and three more to implement the outputs, Y and giving a total of four. The resulting circuit is E P Q R S LUT4 PQ + PQ R U F P Q R S LUT4 (P+QR )S P Q LUT4 R S S +(P Q+PQ +QR) Y P Q R S LUT4 PS(Q +P R) - 4 -

5 7. onsider the circuit shown below. Suppose this circuit is implemented directly, using MOS, with each N gate implemented using a NN and an inverter (similarly for OR gates). What is the worst-case delay for the circuit, assuming that NN and NOR gates have a delay of 1 ns each, and inverters have a delay of.5 ns? Highlight the path through the circuit that accounts for the worst-case delay. U V F G Y The worst-case delay is 5 ns for the highlighted path. Show an alternate implementation, using NNs, NORs and inverters that reduces the delay by at least 1.5 ns. U V F G Y This circuit has a worst-case delay of 3.5 ns from Y to F and from Y to G

6 8. onsider the circuit shown below. ssume that all gates have a minimum propagation delay (for both rising and falling edges) of 1 ns, and a maximum propagation delay of 2 ns. onstruct two timing diagrams showing how all the labeled signals change when input changes from 1 to, while inputs and are held at 1 and, respectively. In the first timing diagram, assume the minimum propagation time for all gates and in the other, assume the maximum propagation time for all gates. raw a third timing diagram which combines the first two, using shading to show the time periods where signal values could be either or 1. uncertainty region

7 9. esign circuits that implement the logic in the truth table shown below. esign two circuits, one which has the smallest possible worst-case propagation delay, and a second which minimizes the gate count. Use only inverters and 2-input N gates and 2-input OR gates. ssume each inverter has a propagation delay of 1 ns and each N and OR gate has a 2 ns propagation delay. When counting gates, treat an inverter as a half-gate. What are the gate counts and worst-case propagation delays for your circuits? = + + = ((+ ) + ) = + + = (+)(+ + ) The first circuit shown corresponds directly to the minimum sum-of-products form of the logic expression and the second to a factorization of the sum-of-products. The first has a gate count of 9 and a worst-case propagation delay of 8 ns, while the second has a gate count of 6 and a worst-case - 7 -

8 propagation delay of 9 ns. However, if we cover the zeros in the K-map to obtain the product-of-sums form, we get a simpler expression, which results in the last circuit shown. This has a gate count of 6 and a worst-case propagation delay of 7 ns, so it is both smallest and fastest. 1. onsider the circuit and timing diagram shown below. ssuming that the inverters are all implemented using MOS technology the output signals and are both a single gate input, which of the two curves labeled with a question mark corresponds to the signal and which to signal? ssume that all the inverters are identical. Explain why this is true.?? The first one corresponds to signal and the second one to signal. The reason for this is that the pull-ups in the pair of inverters driving signal act like a pair of parallel resistors when the input is low. This allows them to pass twice as much current as a single resistor would, so they can pump charge into the output faster, causing the voltage to rise faster