Motivation for Lecture. For digital design we use CMOS transistors. Gate Source. CMOS symboler. MOS transistor. Depletion. A channel is created

Transcription

1 Motivation for Lecture igital Integrated ircuits iktor Öwall o see how standard gates are implemented with transistors? How does technology affect the performance, e.g. speed and power consumption? What has happened with technology scaling? For digital design we use MOS transistors. n + n + N-hannel Solid State Physics I I d S [] Electrical haracteristics gate drain NMOS MOS symboler PMOS igital transistor as a switch source Small Signal Model (amplifier design) gate drain Most common when digital design gs g m gs source g o ds he ulk/substrate is assumed to be connected to / if nothing else specified. ourtesy of Intel MOS transistor N-channel -oxid (isolerande) p - substrat N-channel channel when a positive gate-source voltage,, larger than the threshold voltage is applied,, is applied appliceras. = + γ( 2φF + S 2 φf ) substrat φ = Fermi Potential F epletion > ; e - charge is attracted > channel is created > ; e - laddningar attraheras >, Strong inversion a channel > epletion Region N-kanal epletion Region

2 Linjära Regionen I as a function of S < S < - e - (elektroner) from to Linear Region Increasing S < - > I I x S [] hannel voltage Pinch-off ( x) > GS I as a function of S Pinch-off S = GS When S = - No new charge to the channel he current saturates = S GS - > I I Linear Saturation Slope due to velocity saturation in short channel devices S [] I as a function of Linear Saturation GS G G Kapacitanser t ox S ulk ap. Junction ap. Overlap ap. What is I when =? X d NMOS transistor as a switch PMOS transistor as a switch v in = high a short S [] v in = high a open Increasing v in G S I v in = low a open v in G S v in = low a short S [] I

3 he MOS Inverter MOS Inverter with transistorn as a switch high in a NMOS short PMOS open Out connected to a low MOS Inverter with transistorn as a switch MOS Inverter with transistorn as a switch high in a NMOS short PMOS open low in a NMOS open PMOS short Out connected to a high I he MOS Inverter MOS Inverter Ideal N Off P Lin Real N Sat P Lin N Sat P Sat dd /2 IN N Lin P Sat N Lin P Off IN Logic gates, NN P-hannel N-hannel N-Well P-Substrate ruth able

4 Logic gates, NN Logic gates, NN Logic gates, NN Logic gates, NN Logic gates, NN Logic s, N dd dd NN dd PMOS N NMOS US & Europe NN + Inverter a N f NN NN N f N Logic Function? NN wo Input NN/ N Inverter.8 m MOS

5 Logic Function: NOR his is called omplementary Logic Pull up network Pull down network Properties: + rail to rail swing, i.e.out = or + no static power, i.e. either PUN or PN off - Many transistors US Europe Pseudo-NMOS s Pseudo-NMOS s Pull up network Pull up network Pull down network Properties: + fewer transistors + in the eayrly years there was only NMOS Pull down network - Static power consumption - Low input not Properties: + fewer transistors - Static power consumption - Low input not More complex functions: an adder msb = most signifcant bit a msb b msb a i+ b i+ a i b i lsb = least signifcant bit More complex functions: a carry ripple adder msb = most signifcant bit a msb b msb a i+ b i+ a i b i lsb = least signifcant bit cin msb cin i Max delay cin msb cin i Max delay? cout msb sum msb sum i+ sum i cout msb sum msb sum i+ sum i cout i+ What is the maximum delay? Memory digit cout i+ What is the maximum delay? Memory digit Full dder in MOS, bit o S S 4 bitars adderare and : in : memory in S: sum o : memory out o

6 Speed Power consumption Some properties: L is what we refer to as the process/ technology/ node e.g. 45nm, 32nm, Speed, simplified model pd = k if pd L ( >> L = = k f Reduced capacitance give faster circuits: smaller transistors a less capacitance ) 2 ig approximation today! he distance between and has been reduced. Shouri hatterjee, Yannis sividis and Peter Kinget, nalog ircuit esign echniques at.5 Speed, a simplified model pd = k if pd L ( >> L = = k f Reduced capacitance give faster circuits: smaller transistors, i.e. new technologies a less capacitance lock frequency is proportional to. Why not increase it? Why not decrease? ) 2 ig approximation today! Power consumption in MOS P = P + P + P total dynamic raditionally the most important! short-circuit Gaining more importance with technology scaling static ischarge" ynamic Power onsumption " " harge" P = f 2 dynamic L he 2 does that we especially want to lower a Slower circuits Short ircuit - urrent Spikes urrent peak when both N- and PMOS are open " " Static Power: What is the current when input are stable to high or low? Linear Saturation - I peak

7 due to leakage current Ileakage increases with decreasing " " Pstat =Ileakage! Leakage" Ileakage " " Scaling: and IOFF rade-off Performance vs Leakage:! a ln( IS) Static Power onsumption IOFF! Low High IOFFL IOFFH L H Subthreshold" urrent" G s decreases, sub-threshold leakage increases rends in energy consumption Example from 65nm MOS H Full dder delay(ns) leakage(mw) Nand2 delay(ns) leakage(mw) S L,26,5,,3E-8 2,2E-7,88E-6,39,24,2,94E-9 3,3E-8 2,24E-7 H, S & L: High, standard and low Supply voltage From upcoming book OptimizationSP rchitecture esign Essentials y ejan Markovic (UL) and Robert W. rodersen (U erkeley) So what do we do? H around 45m he end of some scaling! High needed for high speed a High Power consumption! One possibility: parallel processing! Low needed for high speed a High leakage power! wo possibilities: Multiple Find ways to reduce leakage, e.g. power gating Going Multicore, e.g. Intel Sandyridge! Going sub-threshold: long pursued in research. Now: Intel September 2! 32 nm 64 bit ransistors ~3.5 GHz 26 mm2 (x Pentium 4)

8 and new technologies! You can learn more in EIN2 igital I-design. Next week: Storage (registers and memories) omputational platforms esign Methodologies