CHAPTER * 6-2. a) 3-input NAND gate b) 4-input NOR gate * Pearson Education, Inc. a) F = (A + B) C D. b) G = (A + B) (C + D)

Size: px

Start display at page:

Download "CHAPTER * 6-2. a) 3-input NAND gate b) 4-input NOR gate * Pearson Education, Inc. a) F = (A + B) C D. b) G = (A + B) (C + D)"

Joanna Maxwell
6 years ago
Views:

1 HPTER 6 6-.* a) = ( + ) b) G = ( + ) ( + ) 200 Pearson Education, Inc a) 3-input NN gate b) 4-input NOR gate +V +V inputs 6 inputs 6 inputs 6-4.* The longest path is from input or ns ns ns ns = ns 6-5. a) b) c) ns

2 Problem Solutions hapter a) t PHL-, to = 2 t PLH + 2t PHL = 2(0.36) + 2(0.20) =.2 ns t PLH-, to = 2t PHL + 2t PLH = 2(0.20) + 2(0.36) =.2 ns t pd =.2 ns t PHL- to = 2t PHL + t PLH = 2(0.20) + (0.36) = 0.76 ns t PLH- to = 2t PHL + t PLH = 2(0.36) + (0.20) = 0.92 ns t pd- to = = 0.4 ns t PHL-,, to = t PLH + t PHL = = 0.56 ns t PLH -,, to = t PHL + t PLH = = 0.56 ns t pd -,, to = 0.56 ns b) t pd-, to = 4 t pd = 4(0.2) =.2 ns t pd- to = 3 t pd = 3(0.2) = 0.7 ns t pd-,, to = 2 t pd = 2(0.2) = 0.56 ns c) or paths through an odd number of inverting gates with unequal gate t PHL and t PLH, path t PHL, t PLH, and t pd are different. or paths through an even number of inverting gates, path t PHL, t PLH, and t pd are equal If the rejection time for inertial delays is greater than the propagation delay, then an output change can occur before it can be predicted whether or not it is to occur due to the rejection time. or example, with a delay of 2 ns and a rejection time of 3 ns, for a 2.5 ns pulse, the initial edge will have already appeared at the output before the 3 ns has elapsed at which whether to reject or not is to be determined a) The propagation delay is t pd = max(t PHL = 0.05, t PLH = 0.0) = 0.0 ns. ssuming that the gate is an inverter, for a positive output pulse, the following actually occurs: 0.05 ns 0.0 ns If the input pulse is narrower than 0.05 ns, no output pulse occurs so the rejection time is 0.05 ns. The resulting model predicts the following results, which differ from the actual delay behavior, but models the rejection behavior: : 0.0 ns 0.0 ns 9

3 Problem Solutions hapter 6 b) or a negative output pulse, the following actually occurs: 0.5 ns 0.05 ns 0.0 ns The model predicts the following results, which differs from the actual delay behavior and the actual rejection behavior: 0.0 ns 0.0 ns Overall, the model is inaccurate for both cases a and b, and provides a faulty rejection model for case b. Using an average of t PHL and t PLH for t pd would improve the delay accuracy of the model for circuit applications, but the rejection model still fails a)there is a setup time violation at 2 ns. There is an input combination violation around 24 ns. b) There is a setup time violation just before 24 ns, There is an input combination violation around 24 ns. c) There is a setup time violation at 2ns. d) There is a hold time violation at 6ns and a setup time violation at 24ns. 6-0.* a) The longest direct path delay is from input X through the two XOR gates to the output. t delay = t pdxor + t pdxor = = 0.40 ns b) The longest path from an external input to a positive clock edge is from input X through the XOR gate and the inverter to the lip-flop. t delay = t pdxor + t pd INV + t s = = 0.35 ns c) The longest path delay from the positive clock edge is from lip-flop through the two XOR gates to the output. t delay = t pd + 2 t pdxor = (0.20) = 0.0 ns d) The longest path delay from positive clock edge to positive clock edge is from clock on lip-flop through the XOR gate and inverter to clock on lip-flop. t delay-clock edge to clock edge = t pd + t pdxor + t pdinv + t s = = 0.75 ns e) The maximum frequency is /t delay- clock edge to clock edge. or this circuit, t delay-clock edge to clock edge is 0.75 ns, so the maximum frequency is /0.75 ns =.33 GHz. omment: The clock frequency may need to be lower due to other delay paths that pass outside of the circuit into its environment. alculation of this frequency cannot be performed in this case since data for paths through the environment is not provided. 90

4 Problem Solutions hapter a) The longest direct path delay is from input X through the four XOR gates to the output. t delay = 4 t pdxor = 4(0.20) = 0.0 ns b) The longest path from an external input to a positive clock edge is from input X through three XOR gates and the inverter to the clock of the second lip-flop. t delay = 3 t pdxor + t pd INV + t s = 3(0.20) = 0.75 ns c) The longest path delay from the positive clock edge is from the first lip-flop through the four XOR gates to the output. t delay = t pd + 4 t pdxorr = (0.20) =.2 ns d) The longest path delay from positive clock edge to positive clock edge is from the first lip-flop through three XOR gates and one inverter to the clock of the second lip-flop. t delay-clock edge to clock edge = t pd + 3 t pdxor + t pdinv + t s = (0.20) =.5 ns e) The maximum frequency is /t delay-clock edge to clock edge. or this circuit, the delay is.5 ns so the maximum frequency is /.5 ns = 70 MHz. omment: The clock frequency may need to be lower due to other delay paths that pass outside of the circuit into its environment. alculation of this frequency cannot be performed in this case since data for paths through the environment is not provided (7:0) 256 x ROM ddress 256 x ROM ddress EOER x ROM ddress 256 x ROM ddress 256 x ROM ddress 256 x ROM ddress 256 x ROM ddress 256 x ROM ddress (7:0) (5:) 9

5 Problem Solutions hapter * (Errata: hange "32 X " to "64 X " ROM) IN OUT IN OUT IN OUT IN OUT a) = 33 address bits and 6 + = 7 output bits, G 7 b) = address bits and + = 9 output bits c) 4 4 = 6 address bits and 4 output bits are needed, 64K Input Output X X X X X = X + X + = X + X + = = + y using instead of and instead of in, can be shared by all four functions. urther, since is the complement of, terms X and X can be shared between and. Thus, only four product terms, X, X, and are required.n inversion must be programmed for. 92

6 Problem Solutions hapter ind the truth table and K-maps: X E X X X = X = X + = X + X + E X X X = E = 0 = Implementation of,, and E requires only two terms, X and. Straightforward implementation of,, and requires four terms, X, X, X, and. y implementing,, and, only three additional terms X, X, and are required. So we form the solution using five product terms: X,, X, X, and. The solution is described by the equations given with the six K-maps. 6-. The values given in the four K-maps come from Table 3- on page 99. W X d d d d d d d d d d d d d d d d d d 0 d d 0 d d 0 d d W = + X = + + = + = In this case, shared terms are limited. One such term is generated in W. 6-9.* ssume 3-input OR gates. W d d d d d d d d d d d d d d d d d d 0 d d 0 d d 0 d d W = + + X = + + = + = Each of the equations above is implemented using one 3-input OR gate. our gates are used. 93

7 6-20. Problem Solutions hapter 6 igure 6-23 uses 3-input OR gates. X X X X = X + + X = X + + X = + X = X +,, and each require three or fewer product terms so can be implemented with 3-input OR gates. requires four terms so cannot be implemented with a 3-input OR gate. ut because the first PL device output can used as an input to implement other functions it can be assigned to and can then be used to implement using just two inputs of a 3-input OR gate igure 6-23 uses 3-input OR gates. G Straightforward implementation of requires five prime implicants and of G requires four prime implicants, but only 3 inputs are available on the PL OR gates. So sum-of-products that can be factored from and G or both and implemented by the other PL cells are needed. single sum of products that will work is H = + +. The terms of H are shown with dotted lines on the K-maps. Using H: = H + + G = H + There are other possible functions for H and corresponding results for and H. 94

CHAPTER * 2-2.* Pearson Education Limited Problem Solutions, Global Edition Chapter 2. Verification of DeMorgan s Theorem

CHAPTER * 2-2.* Pearson Education Limited Problem Solutions, Global Edition Chapter 2. Verification of DeMorgan s Theorem HPTER 2 2-.* a) XYZ = X + Y + Z Verification of DeMorgan s Theorem Pearson Education Limited 206. X Y Z XYZ XYZ X + Y + Z 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b) X + YZ = ( X + Y) ( X + Z) The Second