Motivation. CS/EE 3700 : Fundamentals of Digital System Design
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1 Motivation CS/EE 37 : Funamentals o Digital System Design Chris J. Myers Lecture 4: Logic Optimization Chapter 4 Algebraic manipulation is not systematic. This chapter presents methos that can be automate in CAD tools. Although tools use or logic optimization, esigners must unerstan the process. Figure 4. The unction = Σ m(, 2, 4, 5, 6) x x 2 m m m 2 m 3 x m m 2 m m 3 (a) Truth table (b) Karnaugh map Figure 4.2 Location o two-variable minterms Figure 2.5 A unction to be synthesize x m m m 2 m 3 m 4 m 5 m 6 m 7 x m m m 3 m 2 m 6 m 7 (b) Karnaugh map m 4 m 5 (a) Truth table Figure 4.4 Location o three-variable minterms
2 x x x x 2 3 m m m 5 m 3 m 2 m 6 m 4 m 2 m 3 m 8 m 9 m 7 m 5 m m 4 m x Figure 4.6 A our-variable Karnaugh map x x 2
3 x x x = 5 x x = 5 Figure 4.8 A ive-variable Karnaugh map Terminology A variable either uncomplemente our complemente is calle a literal. A prouct term that inicates when a unction is equal to is calle an implicant. An implicant that cannot have any literal elete an still be a vali implicant is calle a prime implicant. x x 2 Figure 4.9 Three-variable unction = Σ m(,, 2, 3, 7) Terminology (cont) A collection o implicants that accounts or all input combinations in which a unction evaluates to is calle a cover. An essential prime implicant inclues a minterm covere by no other prime. Cost is number o gates plus number o gate inputs. Assume primary inputs available in both true an complemente orm. Minimization Proceure Generate all prime implicants. Fin all essential prime implicants. I essential primes o not orm a cover, then select minimal set o non-essential primes. 3
4 x x Figure 4. Four-variable unction = Σ m(2, 3, 5, 6, 7,,, 3, 4) Figure 4. The unction = Σ m(, 4, 8,,, 2, 3, 5) x Minimization o POS Forms Fin a cover o the s an orm maxterms. x x x 2 3. Figure 4.2 The unction = Σ m(, 2, 4, 5,,, 3, 5) x x x x Incompletely Speciie Functions Oten certain input conitions cannot occur. Impossible inputs are calle on t cares. A unction with on t cares is calle an incompletely speciie unction. Don t cares can be use to improve the quality o the logic esigne. Figure 4.4 POS minimization o = Π M(,, 4, 8, 9, 2, 5) 4
5 x x Figure 4.5 Two implementations o = Σ m(2, 4, 5, 6, ) + D(2, 3, 4, 5) Figure 4.5 Two implementations o = Σ m(2, 4, 5, 6, ) + D(2, 3, 4, 5) Multiple-Output Circuits Necessary to implement multiple unctions. Circuits can be combine to obtain lower cost solution by sharing some gates. x (a) Function x (b) Function 2 Figure 4.6 An example o multiple-output synthesis x x 2 (c) Combine circuit or an 2 x (a) Optimal realization o 3 (b) Optimal realization o 4 Figure 4.7 An example o multiple-output synthesis x 5
6 x x (c) Optimal realization o 3 an 4 together x x x 3 4 () Combine circuit or 3 an 4 Figure 4.7 An example o multiple-output synthesis x x 3 (a) Function x x 3 (b) Function 2 x (a) Optimal realization o x 3 (b) Optimal realization o 4 x x (a) x = x + x x x x x (b) x + = x x x Figure 4.8 DeMorgan s theorem in terms o logic gates Figure 4.9 Using NAND gates to implement a sum-o-proucts 6
7 x x Multilevel Synthesis x SOP or POS circuits have 2-levels o gates. Only eicient or unctions with ew inputs. Many inputs can lea to an-in problems. Multilevel circuits can also be more area eicient. Figure 4.2 Using NOR gates to implement a prouct-o-sums (rom interconnection wires) x unuse PAL-like block D Q x x A x 6 C x 5 E C B x 7 A B D D E Figure 4.2 Implementation in a CPLD Figure 4.22 Implementation in an FPGA 7 inputs x Figure 4.23 Using 4-input AND gates to realize a 7-input prouct term Figure 4.24 A actore circuit 7
8 Example 4.5 x 2 Figure 4.25 A multilevel circuit Impact on Wiring Complexity Space on chip is use by gates an wires. Wires can be a signiicant portion. Each literal correspons to a wire. Factoring reuces literal count, so it can also reuce wiring complexity. Functional Decomposition Multilevel circuits oten require less area. Complexity is reuce by ecomposing 2-level unction into subcircuits. Subcircuit implements unction that may be use in multiple places. Example 4.6 x g Figure 4.26 A multilevel circuit 8
9 x x x g x g = = h Figure 4.27 The structure o a ecomposition x x x g x (a) Sum-o-proucts implementation k x (b) NAND gate implementation Figure 4.28 An example o ecomposition Figure 4.29 a Implementation o XOR Example 4.8 = x = x + x = x (x + ) + (x + ) x g x (c) Optimal NAND gate implementation Figure 4.29 b Implementation o XOR 9
10 Practical Issues Functional ecomposition can be use to implement general logic unctions in circuits with built-in constraints. Enormous numbers o possible subunctions leas to necessity or heuristic algorithms. x x (a) Circuit with AND an OR gates (b) Inversions neee to convert tonands Figure 4.3 Conversion to a NAND-gate circuit x x (b) Inversions neee to convert tonands x (a) Circuit with AND an OR gates x (a) Inversions neee to convert tonors Figure 4.3 Conversion to a NAND-gate circuit Figure 4.3 Conversion to a NOR-gate circuit x x P P 3 P 4 P 5 x P 2 Figure 4.3 Conversion to a NOR-gate circuit Figure 4.32 Circuit example or analysis
11 x P P 9 x P x P2 x2 P 4 x3 P 3 x3 P 2 P 3 P 7 P 6 P 8 P x4 (a) NAND-gate circuit x4 x5 (b) Moving bubbles to convert to ANDs an ORs P 5 x x2 x3 x4 x5 (c) Circuit with AND an OR gates Figure 4.33 Circuit example or analysis Figure 4.34 Circuit example or analysis x P P 2 P 4 CAD Tools P 3 espresso ins exact an heuristic solutions to the 2-level synthesis problem. sis perorms multilevel logic synthesis. Numerous commercial CAD packages are available rom Caence, Mentor, Synopsys, an others. Figure 4.35 Circuit example or analysis Design conception Design entry, initial synthesis, an unctional simulation (see section 2.8) Logic synthesis/optimization Physical esign Timing simulation No Design correct? Yes Chip coniguration Figure 4.46 A complete CAD system Figure 4.42 VHDL coe or the unction = Σ m(, 4, 5, 6)
12 Physical Design Physical esign etermines how logic is to be implemente in the target technology. Placement etermines where in target evice a logic unction is realize. Routing etermines how evices are to be interconnecte using wires. Figure 4.43 Logic synthesis options in MAX+PLUS II Timing Simulation Functional simulation oes not consier signal propagation elays. Ater physical esign, more accurate timing inormation is available. Timing simulation can be use to check i a esign meets perormance requirements. Figure 4.44 Results o physical esign Design conception Design entry, initial synthesis, an unctional simulation (see section 2.8) (a) Timing in an FPGA Logic synthesis/optimization Physical esign Timing simulation No Design correct? Yes (b) Timing in a CPLD Chip coniguration Figure 4.45 Timing simulation results Figure 4.46 A complete CAD system 2
13 STD_LOGIC type Deine in ieee.st_logic_64 package. Enumerate type with 9 values. strong one strong zero X strong unknown Z high impeence H weak one W weak unknown L weak zero U uninitialize - on t care We will almost always use STD_LOGIC. Figure 4.47 VHDL coe using STD_LOGIC (rom interconnection wires) x unuse PAL-like block D Q Figure 4.48 VHDL coe or the unction = Σ m(, 2, 4, 5, 6) Figure 4.49 Implementation o the VHDL coe or the unction = Σ m(, 2, 4, 5, 6) (rom interconnection wires) x unuse i i 2 i 3 i 4 PAL-like block D Q x i i 2 i 3 i 4 LUT Figure 4.5 Implementation using XOR synthesis ( = x ) Figure 4.5 VHDL coe or = Σ m(, 2, 4, 5, 6) implemente in a LUT 3
14 Figure 4.52 The VHDL coe or = Σ m(2, 3, 9,,, 3) Figure 4.53 VHDL coe or a 7-variable unction x x x x + Logic Function Representation x x (a) Sum-o-proucts realization (b) Factore realization Truth tables Algebraic expressions Venn iagrams Karnaugh maps n-imensional cubes Figure 4.54 Two implementations o a 7-variable unction x x x x x x xx x x x x Figure 4.36 Representation o = Σ m(, 2, 3) Figure 4.37 Representation o = Σ m(, 2, 4, 5, 6) 4
15 n-dimensional Hypercube xx x xx Function o n variables maps to n-cube. Size o a cube is number o vertices. A cube with k x s consists o 2 k vertices. n-cube has 2 n vertices. 2 vertices are ajacent i they ier in one coorinate. Each vertex in n-cube ajacent to n others. Figure 4.38 Representation o = Σ m(, 2, 3, 6, 7, 8,, 5) C = A * B such that. C = i A i * B i = or more than one i. 2. Otherwise, C i = A i * B i when A i * B i an C i = x or the coorinate where A i * B i =. B A i i x x o o x A i * B i Using *-operation to Fin Primes is speciie using a set o cubes, C k o. Let c i an c j be any two cubes in C k. Apply *-operation to all pairs o cubes in C k : G k+ = c i * c j or all c i, c j in C k Form new cover or as ollows: C k+ = C k G k+ reunant cubes A is reunant i exists a B s.t. A i = B i or B i = x or all i. Repeat until C k+ = C k. Figure 4.39 The coorinate *-operation Example 4.4 Example 4.5 5
16 C = A # B, such that. C = A i A i # B i = or some i. 2. C = i A i # B i = ε or all i. 3. Otherwise, C = i (A, A 2,..., B i,... A n ), where the union is or all i or which A i = x an B i x. B A i i x x ε o ε o ε ε ε A i # B i Fining Essential Primes Let P be set o all prime implicants. Let p i enote one prime implicant in P. Let DC enote the on t cares vertices or. Then p i is an essential prime implicant i: p i # (P p i ) # DC Figure 4.4 The coorinate #-operation Example 4.6 Example 4.7 Proceure to Fin Minimal Cover Let C = ON DC be the initial cover o. Fin all primes, P, o C using *-operation. Fin the essential primes using #-operation. I essentials cover ON-set then one else Delete any nonessential prime that is more expensive than some other prime. Use branching technique to select lowest cost primes which cover ON-set. x x = = Figure 4.4 An example our-variable unction 6
17 Summary Describe 2-level logic synthesis methos. Discusse multilevel logic synthesis. Introuce CAD tools or logic synthesis. 7
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