Exclusive OR/ Exclusive NOR

Size: px

Start display at page:

Download "Exclusive OR/ Exclusive NOR"

Vincent Goodman
6 years ago
Views:

1 University of Wisconsin - Madison ECE/Comp Sci 352 Digital Systems Fundamentals Charles R. Kime Section 2 Fall 2001 Chapter 2 Combinational Logic Circuits Part 8 Charles Kime & Thomas Kaminski Exclusive OR/ Exclusive NOR The eclusive OR (OR) function is an important Boolean function used extensively in logic circuits. Uses for the OR gate include: Adders/subtractors Parity generators/checkers Signature analyzers Pseudo-random sequence generators Definitions The OR function is: = + The eclusive NOR (NOR) function, otherwise known as Equivalence is: = + Chapter 2-Part 8 2 1

2 Tables for OR/NOR Operator Rules: OR NOR ( ) or The OR function means: OR, but NOT BOTH The NOR function, denoted by the operator, is also known as the Equivalence function. Why? Chapter 2-Part 8 3 OR/NOR Extension The OR function can be extended to 3 or more variables. For more than 2 variables, it is called a modulo 2 sum (Mod 2 sum), instead of OR: Z = Z + Z + Z + Z The OR definition, Boolean identities and Boolean theorems give: 0 = 1 = = 0 = 1 = = = ( ) Z = ( Z) = Z Chapter 2-Part 8 4 2

3 OR Implementations The simple SOP implementation uses the following structure: A NAND only implementation is: Chapter 2-Part 8 5 OR Implementations (Cont.) The AND-OR implementation is the SOP form for the OR function: = + The multiple-level NAND implementation can be derived by combining inversions as follows: = + = = ( + ) + ( + ) = () + () Chapter 2-Part 8 6 3

4 Odd Function The modulo 2 sum function for n variables Contains an odd number of 1 s, and Is therefore called the odd function. The inverse of the modulo 2 sum function for n variables Contains an even number of 1 s, and Is therefore called the even function. Implementation of even and odd functions for greater than 4 variables as a single gate is difficult, so trees of 2 to 4 input OR or NORs are used. Chapter 2-Part 8 7 Example: Odd Function Implementation Three-Input Odd Function: Four Input Odd Function: Chapter 2-Part 8 8 4

5 Product terms of Odd and Even For an n-bit even or odd function, there will be (2 n )/2 or 2 n 1 w product terms of n variables (minterms)! y z Odd Function x w y z Even Function x v=0 y v=1 x w w z y z x Odd Function of Five Bits Chapter 2-Part 8 9 Parity Generators/Checkers A parity tree for n data bits generates a parity bit that is appended to the data bits to form an n + 1-bit codeword Example: 3-bit even parity generator P A parity tree for n + 1 bits checks the codeword for correct parity: C=0 if the codeword parity is correct C=1 if the codeword parity is correct C Example: 4-bit even Z parity checker P Z Chapter 2-Part

6 Integrated Circuit Parameters Logic device families are characterized by the following parameters: Fan-in the number of inputs available on a gate Fan-out the number of inputs the output of a gate can drive Logic Levels the signal value ranges defining 1 and 0 Propagation Delay The time for an input signal change to propagate to an output Noise Margin the amount of noise a logic signal can tolerate without error Power Supply the voltage(s) require(d) to allow the circuit to operate Power Dissipation the amount of power a circuit consumes Chapter 2-Part 8 11 Propagation Delay Propagation delay is the time for a change in the input of a gate to propagate to the output. Delay is usually measured from the 50% of the logic level voltage reference points. High-to-low (t PHL ) and low-to-high (t PLH ) output signal changes may have different propagation delays. High-to-low ( HL ) and low-to-high ( LH ) transitions are defined with respect to the output, not the input. An HL input transition causes : an LH output transition if the gate inverts and an HL output transition if the gate does not invert. Chapter 2-Part

7 Propagation Delay Example In A B What is the delay for: a string of inverters? a string of buffers? B In A T PHL T PLH T PLH T PHL Chapter 2-Part 8 13 Positive and Negative Logic The same physical gate has different logical meanings depending on interpretation of the signal levels. Positive Logic Logic 1 is set to HIGH (more positive) signal levels Logic 0 is set to LOW (less positive) signal levels Negative Logic Logic 1 is set to LOW (more negative) signal levels Logic 0 is set to HIGH (less negative) signal levels A gate which implements a Positive Logic AND function will implement a Negative Logic OR function. Chapter 2-Part

8 Positive and Negative Logic (Cont.) Given this signal level table: What logic function is implemented? Positive Logic (H = 1) (L = 0) Input L L L H H L H H Negative Logic Output L H H H (H = 0) (L = 1) Chapter 2-Part 8 15 Positive and Negative Logic (Cont.) Rearranging the negative logic terms to be in proper function table order we get: Positive Logic (H = 1) (L = 0) Negative Logic (H = 0) (L = 1) Positive logic "OR", Negative Logic "AND" Chapter 2-Part

9 Logic Symbol Conventions Symbols: CKT Z Logic Circuit Z L L L L H H H L H H H H Z Z Positive Logic Negative Logic Chapter 2-Part

Digital Logic. Lecture 5 - Chapter 2. Outline. Other Logic Gates and their uses. Other Logic Operations. CS 2420 Husain Gholoom - lecturer Page 1

Digital Logic. Lecture 5 - Chapter 2. Outline. Other Logic Gates and their uses. Other Logic Operations. CS 2420 Husain Gholoom - lecturer Page 1 Lecture 5 - Chapter 2 Outline Other Logic Gates and their uses Other Logic Operations CS 2420 Husain Gholoom - lecturer Page 1 Digital logic gates CS 2420 Husain Gholoom - lecturer Page 2 Buffer A buffer