Menu. Binary Adder EEL3701 EEL3701. Add, Subtract, Compare, ALU

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1 Other MSI Circuit: Adders >Binar, Half & Full Canonical forms Binar Subtraction Full-Subtractor Magnitude Comparators >See Lam: Fig 4.8 ALU Menu Look into m... 1 Binar Adder Suppose we want to add two 2-bit numbers Sum Carr Carr Sum = /X Y + X /Y = X Y Carr = X Y 2 1

2 Notation for Binar Addition Notation: A 4-bit number is represented b b 3 b 2 b 1 b 0. Thus, we get bits b 0 ~b N-1 where N = # of bits. If we add two 4-bit numbers, what must we do bit b bit? c 3 c 2 c 1 c 0 = 0 c i = carr bit i = 1 st number i = 2 nd number c 4 s 3 s 2 s 1 s 0 s i = sum For the circuit with no carr in, we implement as follows: i s i i s i = i i c i+1 = i i c i+1 This circuit is called a Half-Adder 3 Adder with Carr Input Let us include a carr input ( ) in the design: Sum = /*/* + /* */ + */*/ + * * Sum c out When = 0, Sum cin =0 = When = 1, Sum cin =1 = /( ) Sum = Sum cin =1 + Sum cin =0 / Sum = /( ) + ( ) / Let W= Then Sum = /W + W / = W Sum = 4 2

3 Let s do C out : c out Q: Is the order important? Q: Wh? Carr Out of Full Adder Sum of all possible pairs c out = + + Sum = s i = c i & c out = c i+1 Sum c out XOR of all inputs Sum= i i c i Canonical.cct This circuit is called a Full-Adder s FA c o s i c i+1 5 Y 3 X 3 C 3 Ripple-Carr Adders Thus, to add two 4-bit numbers we need 4 Full- Adders as follows: Y 2 X 2 C 2 Y 1 X 1 C 1 Y 0 X 0 C 0 =0 FA 0 (C 0 =0) FA 3 FA 2 FA OR 1 HA (no C 0 ) C 4 S 3 C 3 S 2 C 2 S 1 C 1 S 0 Actuall, we could replace FA 0 with a half-adder is a 4-bit look-ahead carr adder 6 3

4 Levels of Logic What if ou don t have XOR gates? X Y = /X Y + X /Y /X Two level logic Y X X Y /Y If ou need 3-input adder (and 3-input XOR), then: X Y C i Four level logic...wh? X Y C i 7 Sum Circuit But from K-map (or truth table) we can implement as sum of 4 minterms. Sum = /*/* + /* */ + */*/ + * * = What if ou onl have NAND gates? AND-OR Canonical.cct NAND-NAND 8 4

5 Canonical Forms: AND-OR = NAND-NAND MSOP = Minimum Sum of Product = An OR of AND terms good (mied-logic) form bad (P-logic) form Canonical.cct 9 c out Addition Eample Eample: Let c out = + + good (miedlogic) form c out Similarl, MPOS: OR-AND = NOR-NOR good (miedlogic) form bad (P-logic) form Canonical.cct c out bad (P-logic) form 10 5

6 Binar Subtraction If we subtract two 4-bit numbers, what must we do bit b bit? b 3 b 2 b 1 b 0 = 0 b i = borrow in m 3 m 2 m 1 m 0 m i = minuend s 3 s 2 s 1 s 0 s i = subtrahend b 4 d 3 d 2 d 1 d 0 d i = difference Consider the following: B i M i S i D i m i s i b i = =-3 FS d i b i+1 11 Subtraction Equations d i = m i s i b i b i+1 = /m i s i + /m i b i + s i b i d i b i+1 For a full adder we had previousl: s i = i i c i c i+1 = i i + i c i + i c i 12 6

7 Full Subtractor using Full Adder Suppose we let i =/m i in the Full Adder equation s i = i i c i then s i = /m i i c i c i+1 = i i + i c i + i c i then c i+1 = /m i i + /m i c i + i c i /s i = m i i c i then d i = /s i = m i s i b i m i s i b i i s i c i b i b i+1 = /m i s i + /m i b i + s i b i s i FS c i+1 d i b i+1 m i s i b i s i FA c i+1 Same! d i b i+1 13 FS using FA and K-maps Can also derive the same result using K-maps: >Let a i =/m i, b i =s i & c i =b i sum /diff /diff carr borrow K-maps for a FS for /d i and b i+1 m i s i d i m i i s i s i FS b c i+1 b i i+1 s i i FA b c i i c i+1 Alternative: Change m i and d i to active-low d i b i

8 We want a device to compare two binar numbers A & B and tell us: > (1) if A > B > (2) if A < B > (3) if A=B A A>B 2 A=B B 2 A<B Lam: Fig. 4.7 Magnitude Comparators 15 Magnitude Comparator K-Map We want a device to compare two binar numbers A & B and tell us: > (1) if A > B (2) if A < B (3) if A=B A A>B 2 A=B B 2 A<B Lam: Fig

9 2-bit Magnitude Comparator Realization Lam: Fig A A>B B 4 4-bit Magnitude Comparators 4 A=B A<B Suppose A & B are 4 bit numbers. What is the corresponding size of the K-Map? A = a 3 a 2 a 1 a 0 B = b 3 b 2 b 1 b 0 Hence, 8 inputs! 8-variable K-Map is a mess! (A=B) = /(A>B) /(A<B) (A>B) = /(A=B) /(A<B) (A<B) = /(A>B) /(A=B) It takes 2 independent outputs and we can get the third from the 2. Note: A = B cannot be simplified. A>B or A<B seem (and are) rotations/reflections of the same map. 18 9

10 4-bit Mag Comparator (74 85) 4 A 4 B (A>B) OUT (A=B) OUT (A<B) OUT Cascading comparators (A>B) IN (A=B) IN (A<B) IN See Lam: Fig bit Mag Comparator (74 85) See Lam: Fig A 4 B (A>B) IN (A=B) IN (A<B) IN (A>B) OUT (A=B) OUT (A<B) OUT 20 10

11 Arithmetic-Logic Units (ALU s) ALU s are at the heart of CPU s - The are the combinational circuit elements that perform common functions: A set of logical functions & a set of arithmetic functions. See figures on net 2 pages [Eample] Let a computer instruction to complement the A register be COMA. The instruction COMA must do the following 3 things: (a) Connect the output of the A register to the A input of the ALU. (b) Present the ALU with control signals: M = H, S 0 = L, S 1 = L, S 2 = L, and S 3 = L. (c) Wait an appropriate dela and connect the output of the ALU (F 3 -F 0 ) to the input of the A register to reload the A register. 21 Lam Fig 6.1 ALU (74 181) Active-High View 22 11

12 Lam Fig 6.1 ALU (74 181) Active-Low View 23 Arithmetic-Logic Units (ALU s) ALU s are at the heart of CPU s - The are the combinational circuit elements that perform common functions: A set of logical functions & a set of arithmetic functions. See figures on previous 2 pages [Eample] Let a computer instruction to complement the A register be COMA. The instruction COMA must do the following 3 things: (a) Connect the output of the A register to the A input of the ALU. (b) Present the ALU with control signals: M = H, S 0 = L, S 1 = L, S 2 = L, and S 3 = L. (c) Wait an appropriate dela and connect the output of the ALU (F 3 -F 0 ) to the input of the A register to reload the A register

13 ALU Lab During development, ou can use a functional compile or simulation or otherwise, ou can let Quartus choose the device >This will allow ou to add etra outputs to aid in debugging If ou let Quartus choose the device, compiling will take a LONG time. So do NOT do it! But ou could pick a bigger device during development Make a table of instructions for each of the prelab requirements 25 The End! 26 13