Outcomes. Spiral 1 / Unit 2. Boolean Algebra BOOLEAN ALGEBRA INTRO. Basic Boolean Algebra Logic Functions Decoders Multiplexers
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1 piral / Unit 2 Basic Boolean Algebra Logic Functions Decoders Multipleers Mark Redekopp Outcomes I know the difference between combinational and sequential logic and can name eamples of each. I understand latenc, throughput, and at least technique to improve throughput I can identif when I need state vs. a purel combinational function I can convert a simple word problem to a logic function (TT or canonical form) or state diagram I can use Karnaugh maps to snthesie combinational functions with several outputs I understand how a register with an enable functions & is built I can design a working state machine given a state diagram I can implement small logic functions with comple CMO gates -2.3 Boolean Algebra -2.4 A set of theorems to help us manipulate logical epressions/equations Aioms = Basis / assumptions used Theorems = manipulations that we can use BOOLEAN ALGEBRA INTRO
2 Aioms -2.5 Dualit -2.6 Aioms are the basis for Boolean Algebra Notice that these aioms are simpl restating our definition of digital/binar logic A/A = Binar variables (onl 2 values possible) A2/A2 = NOT operation A3,A4,A5 = AND operation A3,A4,A5 = OR operation Ever truth statement can ields another truth statement I eercise if I have time and energ (original statement) I don t eercise if I don t have time or don t have energ (dual statement) To epress the dual, swap (A) X = if X (A ) X = if X (A2) If X =, then X = (A2 ) If X =, then X = (A3) = (A3 ) + = (A4) = (A4 ) + = (A5) = = (A5 ) + = + = Dualit -2.7 ingle Variable Theorems -2.8 The dual of an epression is not equal to the original + Original epression Taking the dual of both sides of an equation ields a new equation X + = Original equation Dual X = Dual Provide some simplifications for epressions containing: a single variable a single variable and a constant bit Each theorem has a dual (another true statement) Each theorem can be proved b writing a truth table for both sides (i.e. proving the theorem holds for all possible values of X) T X + = X T' X = X T2 X + = T2' X = T3 X + X = X T3' X X = X T4 (X')' = X T5 X + X' = T5' X X' =
3 ingle Variable Theorem (T) ingle Variable Theorem (T2) X+ = X (T) X = X (T ) X+ = (T2) X = (T2 ) X Z Hold constant X Z X Z Hold constant X Z OR AND OR AND Whenever a variable is OR ed with, the output will be the same as the variable OR Anthing equals that anthing Whenever a variable is AND ed with, the output will be the same as the variable AND Anthing equals that anthing Whenever a variable is OR ed with, the output will be OR anthing equals Whenever a variable is AND ed with, the output will be AND anthing equals ingle Variable Theorem (T3) ingle Variable Theorem (T4) X+X = X (T3) X X = X (T3 ) (X ) = X (T4) (X) = X (T4) X Z OR Whenever a variable is OR ed with itself, the result is just the value of the variable X Z AND Whenever a variable is AND ed with itself, the result is just the value of the variable This theorem can be used to reduce two identical terms into one OR to replicate one term into two. Anthing inverted twice ields its original value
4 ingle Variable Theorem (T5) Application: Channel elector X+X = (T5) X Z OR Whenever a variable is OR ed with its complement, one value has to be and thus the result is X X = (T5 ) X Z AND Whenever a variable is AND ed with its complement, one value has to be and thus the result is This theorem can be used to simplif variables into a constant or to epand a constant into a variable. Given 4 input, digital music/sound channels and 4 output channels Given individual select inputs that select input channel to be routed to output channel 4 Input channels ICH ICH ICH2 ICH3 Input Channel elect IEL IEL IEL2 IEL3 Channel elector OEL OEL OEL2 OEL3 OCH OCH OCH2 OCH3 Output Channel elect 4 Output channels Application: teering Logic Application: teering Logic 4 input music channels (ICH) elect one input channel (use IEL inputs) Route to one output channel (use OEL inputs) ICH ICH ICH 2 ICH 3 OCH OCH OCH 2 OCH 3 st Level of AND gates act as barriers onl passing channel OR gates combines 3 streams of s with the channel that got passed (i.e. ICH) 2 nd Level of AND gates passes the channel to onl the selected output ICH ICH ICH 2 ICH 3 ICH Connection Point ICH ICH ICH ICH ICH OCH OCH OCH 2 ICH OCH 3 IEL IEL IEL2 IEL3 OEL OEL OEL2 OEL3 AND: AND ICH = ICH AND ICH = IEL IEL IEL2 IEL3 OR: + ICH + + = ICH OEL OEL OEL2 OEL3 AND: AND ICH = ICH AND ICH =
5 our Turn Build a circuit that takes 3 inputs:, IN, IN and outputs a single bit. It s functions should be: If =, = IN (IN passes to ) If =, = IN (IN passes to ) IN CHECKER / DECODER IN Gates Gates can have more than 2 inputs but the functions sta the same AND = output = if ALL inputs are Outputs for onl input combination OR = output = if AN input is Outputs for onl input combination s / Decoders An AND gate onl outputs for combination That combination can be changed b adding inverters to the inputs We can think of the AND gate as checking or decoding a specific combination and outputting a when it matches. X Z F X Z F X Z F X Z F F F F F 3-input AND 3-input OR AND gate decoding (checking for) combination AND gate decoding (checking for) combination
6 s / Decoders s / Decoders Place inverters at the input of the AND gates such that F produces onl for input combination {,,} = {} G produces onl for input combination {,,} = {} An OR gate onl outputs for combination That combination can be changed b adding inverters to the inputs AND gate decoding (checking for) combination F X Z F AND gate decoding (checking for) combination G X Z G Add inverters to create an OR gate decoding (checking for) combination F X Z F Add inverters to create an OR gate decoding (checking for) combination F X Z F Design an instruction decoder that uses opcode[5:] and func[5:] as inputs and produces a separate output {ADD, RL, UB, etc.} for each instruction tpe that will produce '' when that instruction is loaded Decoder Eercise R-Tpe I-Tpe J-Tpe opcode rs rt rd shamt func ADD $8 $7 $5 RL $8 $7 $5 7 UB $8 $7 $5 7 opcode rs rt immediate ADDI $24 $5 2 LW $3 $5 W $3 $5 BEQ $3 $5 opcode Jump address Jump address J 26-bits Decoder Eercise ADD RL UB J-Tpe I-Tpe R-Tpe opcode rs rt rd shamt ADD $8 $7 $ func RL $8 $7 $5 7 UB $8 $7 $5 7 opcode rs rt immediate ADDI $24 $5 2 LW $3 $5 W $3 $5 BEQ $3 $5 opcode Jump address Jump address J 26-bits
7 Decoder Eercise ADDI LW W J-Tpe I-Tpe R-Tpe opcode rs rt rd shamt ADD $8 $7 $ func RL $8 $7 $5 7 UB $8 $7 $5 7 opcode rs rt immediate ADDI $24 $5 2 LW $3 $5 W $3 $5 BEQ $3 $5 opcode Jump address Jump address J 26-bits PC 4 A B + Addr. Instruc. I-Cache [25:] [5:] [3:26] [5:] RegDst ingle Ccle CPU h. 26 Left 2 28 [2:6] Reg. # Reg. 2 # Write Reg. # Write Data data data 2 Register File 32 Jump Mem & MemWrite ALUOp[:] MemtoReg Control RegDst ALUrc RegWrite [25:2] 6 ign Etend 32 INT[5:] ALUOp[:] Jump Address = {NewPC[3:28], INT[25:],} h. Left 2 Branch Net Instruc. Address ALU + Zero Res. ALUrc ALU control Branch Address PCrc 26 Mem Addr. Data Write Data D-Cache MemWrite Jump MemtoReg Full Decoders Decoders A full decoder is a building block that: Takes in an n bit binar number as input Decodes that binar number and activates the corresponding output Individual outputs for EVER (MOT) input combination (i.e. 2 n outputs) A decoder is a building block that: Takes a binar number as input Decodes that binar number and activates the corresponding output Put in 6=, Output 6 activates ( ) Put in 5=, Output 5 activates ( ) 3-bit binar number 3-to Decoder output for each combination of the input number Binar #6 Onl that numbered output is activated
8 Decoders Decoder ies A decoder is a building block that: Takes a binar number as input Decodes that binar number and activates the corresponding output Put in 6=, Output 6 activates ( ) Put in 5=, Output 5 activates ( ) Binar #5 Onl that numbered output is activated A decoder w/ an n bit input has 2 n outputs output for ever combination of the n bit input (MB) n inputs (2) 2-to-4 Decoder 2 n outputs (4) n inputs (3) (MB) 3-to Decoder 2 n outputs (8) Eercise Building Decoders Complete the design of a 2 to 4 decoder for O for O D for O2 D D2 3-bit number [A2:A] for for for O3 O4 O5 D3 for O6 for O7
9 Enables Enables Eactl one output is active at all times It ma be undesirable to alwas have an active output Add an etra input (called an enable) that can independentl force all the outputs to their inactive values When E=, inputs is ignored ince E=, all outputs = 2-to-4 Decoder One output will alwas be active Will force all outputs to when E = (i.e. not enabled) When E=, inputs will cause the appropriate output to go active ince E=, outputs will function normall Implementing Enables Enables Original 2 to 4 decoder Enables can be implemented b connecting it to each AND gate of the decoder A A B B A A B B A D A D D D B D2 B D2 D3 D3 E When E=, force all outputs = When E=, outputs operate as the did originall E When E=, AND anthing = When E=, AND anthing = that anthing, which was the normal decoding logic
10 Multipleers Multipleers Along with adders, multipleers are most used building block n data inputs, log 2 n select bits, output A multipleer ( mu for short) selects one data input and passes it to the output n data inputs 4-to- Mu i i i2 i3 output 2 Thus, input 2 = C[3:] is selected and passed to the output A[3:] B[3:] C[3:] D[3:] 4-to- Mu i i i2 i3 s elect bits = 2 = 2. C[3:] s log 2 n select bits Multipleers Multipleers 4-to- Mu 2-to- Mu 2 Thus, input = A[3:] is selected and passed to the output A[3:] B[3:] C[3:] D[3:] i i i2 i3 s A[3:] 2 Thus, input = B[3:] is selected and passed to the output A[3:] B[3:] i i s B[3:] elect bits = 2 =. elect bits = 2 =.
11 Recall Using T/T2 Eercise: Build a 4 to mu st Level of AND gates act as barriers onl passing channel OR gates combines 3 streams of s with the channel that got passed (i.e. ICH) 2 nd Level of AND gates passes the channel to onl the selected output Essentiall this logic forms a 4-to- mu where one level of gates blocks all but and then the OR gate combines all signals ICH ICH ICH 2 ICH 3 ICH Connection Point ICH ICH ICH ICH ICH OCH OCH OCH 2 ICH OCH 3 Complete the 4 to mu to the right b drawing wires between the 2 to 4 decode and the AND gates I I I 2 I 3 = = = = AND Gates acting as barrier gates Final OR gate takes 3 ero s and one selected input AND: AND ICH = ICH AND ICH = IEL IEL IEL2 IEL3 OR: + ICH + + = ICH OEL OEL OEL2 OEL3 AND: AND ICH = ICH AND ICH = 2-to-4 Decoder Building a Mu Building a Mu To build a mu Decode the select bits and include the corresponding data input. Finall OR all the first level outputs together. To build a mu Decode the select bits and include the corresponding data input. Finall OR all the first level outputs together. I I I = 2 I I 2 I I I I 3
12 Building a Mu Building Wide Mues To build a mu Decode the select bits and include the corresponding data input. Finall OR all the first level outputs together. = 2 I I I 2 I 3 o far mues onl have single bit inputs I is onl bit I is onl bit What if we still want to select between 2 inputs but now each input is a 4 bit number Use a 4 bit wide 2 to mu B I A I I I -bit wide 2-to- mu Pass all 4 bits When we select I of I or I or I we want all 4-bits of that input to be passed I 3 g I 3 I 3 4-bit wide 2-to- mu Building Wide Mues Building Wide Mues To build a 4 bit wide 2 to mu, use 4 separate 2 to mues When =, all mues pass their I inputs which means all the A bits get through When =, all mues pass their I inputs which means all the B bits get through In general, to build an m bit wide n to mu, use m individual (separate) n to mues A A A2 A3 B B B2 B3 I I I I I I I I 2 3 To build a 4 bit wide 2 to mu, use 4 separate 2 to mues When =, all mues pass their I inputs which means all the A bits get through When =, all mues pass their I inputs which means all the B bits get through In general, to build an m bit wide n to mu, use m individual (separate) n to mues A A A2 A3 B B B2 B3 A B A B A2 B2 A3 B3 I I I I I I I I 2 3
13 Eercise ingle Ccle CPU How man bit wide mues and of what sie would ou need to build a 4 to, 8 bit wide mu (i.e. there are 4 numbers: W[7:], X[7:], [7:] and Z[7:] and ou must select one) How man bit wide mues and of what sie would ou need to build a 8 to, 2 bit wide mu? PC 4 A B + Addr. Instruc. I-Cache [25:] [5:] [3:26] h. 26 Left 2 28 [2:6] [5:] RegDst Reg. # Reg. 2 # Write Reg. # Write Data data data 2 Register File 32 Jump Mem & MemWrite ALUOp[:] MemtoReg Control RegDst ALUrc RegWrite [25:2] 6 ign Etend 32 INT[5:] ALUOp[:] Jump Address = {NewPC[3:28], INT[25:],} h. Left 2 Branch Net Instruc. Address ALU + Zero Res. ALUrc ALU control Branch Address PCrc Mem Addr. Data Write Data D-Cache MemWrite Jump MemtoReg Building Large Mues -2.5 Design an 8 to mu with 2 to Mues imilar to a tournament of sports teams Man teams enter and then are narrowed down to winner In each round winners pla winners I I I2 I3 I I I I I I I I4 I I5 I I I I I6 I I7 I
14 Cascading Mues Building a 4 to Mu Use several small mues to build large ones Rules. Arrange the mues in stages (based on necessar number of inputs in st stage) 2. Outputs of stage feed to inputs of the net 3. All mues in a stage connect to the same group of select bits Usuall, LB connects to first stage MB connect to last stage D D D 2 D 3 tage tage 2 I I I I Rule : Outputs from stage connect to inputs of stage 2 I I 4-to- mu built w/ 2-to- mues Rule 2: LB connect to all mues in first stage. MB connects to all mues in second stage Building a 4 to Mu Building a 4 to Mu tage tage 2 tage tage 2 D D D 2 D D I I I D D D 2 D D I I D I D 3 Walk through an eample: = D 2 D 3 I I I D 3 Walk through an eample: = D 2 D 3 I I D 3 I = narrows our choices down to D and D 3
15 Building a 4 to Mu Eercise D D tage tage 2 D I D I D I Create a 3 to mu using 2 to mues Inputs: I, I, I2 and select bits, Output: D 2 D D 3 Walk through an eample: = D 2 D 3 I I D 3 I = selects our final choice, D
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