BCD-TO-DECIMAL DECODER HIGH-VOLTAGE SILICON-GATE CMOS IW4028B TECHNICAL DATA
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1 TECHNICAL DATA BCD-TO-DECIMAL DECODER HIGH-OLTAGE SILICON-GATE CMOS IW4028B The IW4028B types are BCD-to-decimal or binary-tooctal decoders consisting of buffering on all 4 inputs, decoding-logic gates, and output buffers. A BCD code applied to the four inputs, A0 to A3 results in a high level at the selected one of decimal decoded outputs. Similarly, a 3-bit binary code applied to inputs A0 through A2 is decoded in octal code at output 0 to7 if A3= 0. High drive capability is provided at all outputs to enhance dc and dynamic performance in high fan-out applications. FEATURES BCD-to-decimal decoding or binary-to-octal decoding Operating oltage Range: 3.0 to 18 Maximum input current of 1 A at 18 over full package-temperature range; 0 na at 18 and 25 C Noise margin (over full package temperature range): 1.0 supply 2.0 supply 2.5 supply ORDERING INFORMATION IW4028BN Plastic IW4028BD SOIC T A = -55 to 125 C for all packages PIN ASSIGNMENT ORDERING INFORMATION Device Operating Temperature Range Package Packing IW4028BN DIP 16 Tube IW4028BD Т А = С SOP16 Tube IW4028BDT SOP16 Tape & Reel LOGIC DIAGRAM PIN 16= CC PIN 8= GND February, er. 00
2 MAXIMUM RATINGS * Symbol Parameter alue Unit CC DC Supply oltage (Referenced to GND) -0.5 to +20 IN DC Input oltage (Referenced to GND) -0.5 to CC +0.5 OUT DC Output oltage (Referenced to GND) -0.5 to CC +0.5 I IN DC Input Current, per Pin ma P D Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ P D Power Dissipation per Output Transistor 0 mw Tstg Storage Temperature -65 to +0 C T L Lead Temperature, 1 mm from Case for Seconds (Plastic DIP or SOIC Package) 260 C * Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. + Derating - Plastic DIP: - mw/ C from 65 to 125 C SOIC Package: - 7 mw/ C from 65 to 125 C mw RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit CC DC Supply oltage (Referenced to GND) IN, OUT DC Input oltage, Output oltage (Referenced to GND) 0 CC T A Operating Temperature, All Package Types C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, IN and OUT should be constrained to the range GND ( IN or OUT ) CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or CC ). Unused outputs must be left open February, er. 00
3 DC ELECTRICAL CHARACTERISTICS (oltages Referenced to GND) Symbol Parameter Test Conditions IH IL OH OL I IN I CC I OL I OH Minimum High-Level Input oltage Maximum Low -Level Input oltage Minimum High-Level Output oltage Maximum Low-Level Output oltage Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Minimum Output Low (Sink) Current Minimum Output High (Source) Current OUT = 0.5 or CC OUT = 1.0 or CC OUT = 1.5 or CC OUT = 0.5 or CC OUT = 1.0 or CC OUT = 1.5 or CC CC IN =GND or CC IN =GND or CC Guaranteed Limit -55 C 25 C 125 C Unit IN = GND or CC A IN = GND or CC 20 IN = GND or CC OL =0.4 OL =0.5 OL =1.5 IN = GND or CC OH =2.5 OH =4.6 OH =9.5 OH = A ma ma February, er. 00
4 AC ELECTRICAL CHARACTERISTICS (C L =50pF, R L =200k, Input t r = t f = 20 ns) Symbol Parameter CC Guaranteed Limit -55 C 25 C 125 C Unit t PHL, t PLH Maximum Propagation Delay, Input A to Output Y (Figure 1) ns t THL, t TLH Maximum Output Transition Time, Any Output (Figure 1) ns C IN Maximum Input Capacitance pf FUNCTION TABLE Inputs Outputs A3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 L L L L H L L L L L L L L L L L L H L H L L L L L L L L L L H L L L H L L L L L L L L L H H L L L H L L L L L L L H L L L L L L H L L L L L L H L H L L L L L H L L L L L H H L L L L L L L H L L L L H H H L L L L L L L H L L H L L L L L L L L L L L H L H L L H L L L L L L L L L H H L H L L L L L L L L L L L H L H H L L L L L L L L L L H H L L L L L L L L L L L L H H L H L L L L L L L L L L H H H L L L L L L L L L L L H H H H L L L L L L L L L L February, er. 00
5 Figure 1. Switching Waveforms EXPANDED LOGIC DIAGRAM Figure February, er. 00
6 PACKAGE DIMENSION N SUFFIX PLASTIC (MS - 001BB) A 16 1 G F 0.25 (0.0) M T 9 8 D N B -T- C -T- NOTES: 1. imensions A, B do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.0) per side. K SEATING PLANE M L H J Dimensions, mm Symbol MIN MAX A B C 5.33 D F G 2.54 H 7.62 J 0 K L M N 0.38 D SUFFIX SOIC (MS - 012AC) H 16 1 D G A 0.25 (0.0) M T C M 9 8 NOTES: 1.Dimensions A and B do not include mold flash or protrusion. 2.Maximum mold flash or protrusion 0. mm (0.006) per side for A, for B mm (0.0) per side. B K P C SEATING PLANE J R x 45 F M Dimensions, mm Symbol. MIN MAX A B C D F G 1.27 H 5.72 J 0 8 K M P R February, er. 00
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CD4071BC CD4081BC Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate
Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate General Description The CD4071BC and CD4081BC quad gates are monolithic complementary MOS (CMOS) integrated circuits cotructed
UNISONIC TECHNOLOGIES CO., LTD
UNISONIC TECHNOLOGIES CO., LTD SINGLE 2-LINE TO 1-LINE DATA SELECTOR OR MULTIPLEXER DESCRIPTION The U74LC2G157 is a single 2-line to 1-line data selector or multiplexer which is featured a common strobe
KK74HC221A. Dual Monostable Multivibrator TECHNICAL DATA PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE
TECNICAL DATA KK74C22A Dual Monostable Multivibrator The KK74C22A is identical in pinout to the LS/ALS22. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible
Features Y Wide supply voltage range 3 0V to 15V. Y High noise immunity 0 45 VDD (typ ) Y Low power TTL fan out of 2 driving 74L
CD4025 CD4023BM CD4023BC Buffered Triple 3-Input NAND Gate CD4025BM CD4025BC Buffered Triple 3-Input NOR Gate General Description These triple gates are monolithic complementary MOS (CMOS) integrated circuits
Obsolete Product(s) - Obsolete Product(s)
DUAL BINARY TO 1 OF 4 DECODER/DEMULTIPLEXER OUTPUT LOW ON SELECT EXPANDABLE WITH MULTIPLE PACKAGES STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIFIED UP TO 20V 5V, 10V AND 15V
HCF4555B DUAL BINARY TO 1 OF 4 DECODER/DEMULTIPLEXER OUTPUT HIGH ON SELECT
DUAL BINARY TO 1 OF 4 DECODER/DEMULTIPLEXER OUTPUT HIGH ON SELECT EXPANDABLE WITH MULTIPLE PACKAGES STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIFIED UP TO 20V 5V, 10V AND 15V
CD4013BC Dual D-Type Flip-Flop
Dual D-Type Flip-Flop General Description The CD4013B dual D-type flip-flop is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement mode transistors. Each
UNISONIC TECHNOLOGIES CO., LTD
U74LC1G04 UNISONIC TECHNOLOGIES CO., LTD SINGLE INERTER GATE DESCRIPTION The UTC U74LC1G04 is a single inverter gate, it provides the function Y = A. This device has power-down protective circuit, preventing
NTE4501 Integrated Circuit CMOS, Dual 4 Input NAND Gate, 2 Input NOR/OR Gate, 8 Input AND/NAND Gate
NTE4501 Integrated Circuit CMOS, Dual 4 Input NAND Gate, 2 Input NOR/OR Gate, 8 Input AND/NAND Gate Description: The NTE4501 is a triple gate device in a 16 Lead DIP type package constructed with MOS P
CD4028BM CD4028BC BCD-to-Decimal Decoder
CD4028BM CD4028BC BCD-to-Decimal Decoder General Description The CD4028BM CD4028BC is a BCD-to-decimal or binaryto-octal decoder consisting of 4 inputs decoding logic gates and 10 output buffers A BCD
CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset
October 1987 Revised January 1999 CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset General Description The CD4027BC dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits
CD4049UBC CD4050BC Hex Inverting Buffer Hex Non-Inverting Buffer
CD4049UBC CD4050BC Hex Inverting Buffer Hex Non-Inverting Buffer General Description The CD4049UBC and CD4050BC hex buffers are monolithic complementary MOS (CMOS) integrated circuits constructed with
NTE74HC109 Integrated Circuit TTL High Speed CMOS, Dual J K Positive Edge Triggered Flip Flop w/set & Reset
NTE74HC109 Integrated Circuit TTL High Speed CMOS, Dual J K Positive Edge Triggered Flip Flop w/set & Reset Description: The NTE74HC109 is a dual J K flip flip with set and reset in a 16 Lead plastic DIP
74HC of 8 Decoder/ Demultiplexer. High Performance Silicon Gate CMOS
of 8 Decoder/ Demultiplexer High Performance Silicon Gate CMOS The 74HC38 is identical in pinout to the LS38. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are