A Mathematical Solution to. by Utilizing Soft Edge Flip Flops

Transcription

1 A Mathematical Solution to Power Optimal Pipeline Design by Utilizing Soft Edge Flip Flops M. Ghasemazar, B. Amelifard, M. Pedram University of Southern California Department of Electrical Engineering August 11, 2008 ISLPED

2 Outline Soft-Edge Flip Flops Power Optimal Pipeline Design Problem Formulation SEFF Modeling Experimental Results Conclusion 2

3 Soft Edge Flip Flop Key idea: Allow the data to pass through a flip flop during a transparency window, instead of on a triggering clock edge Key advantage: Enable slack passing between adjacent pipeline stages which separated by (master-slave) flipflops oware Circuit implementation: Delay the clock of the master latch to create a window during which both the master and slave latches are ON D Setup Time D Q SEFF CLK Tr ransparency Windo Hold Time DATA 3

4 SEFF Implementation Conventional (Hard Edge) D Q Master-Slave FF Soft Edge D D Q Master-Slave FF D D D Delay D D 4

5 SEFF Characteristics Setup and hold times, and clock-to-q delay of a soft-edge flip-flop are all functions of the transparency window width, w Simulations show a linear dependency on w t ( w ) = a w + a thi, ( wi ) = b1 wi + b0 tcq i( wi ) = c wi + c si, i 1 i 0, 1 0 Time (ps) Setup/Hold Setup Time y = 0.921x Hold -40 Time y = x Window size (ps) 5

6 SEFF Characteristics cont d Power consumption of a SEFF is monotonically increasing with its window size (w). This is due to: Higher switching activities in the internal nodes in the transparency window Higher dynamic and leakage power consumption in the additional delay generation circuitry Experimental evaluation of total power consumption: 2 FF, i = 2 i + 1 i + 0 P d w d w d Power Dissipa ation (uw) Transparency window (ps) 6

7 Pipeline Basics CLK D Q D Q D Q FF0 C1 FF1 C2 FF2 t cq,i d i t s,i Timing constraints for a linear pipeline d + t + t T i N δ i s, i cq, i 1 clk 1 + t t i N i cq, i 1 hi, 1 Substitute FFs with SEFFs (1) (2) First and Last FF s remain hard-edge ones This is needed to avoid imposing constraints on the sender/receiver of data Intermediate stage FF s may be substituted by SEFFs d T t ( w ) t ( w ) 1 i N i clk s, i i cq, i 1 i 1 δi hi, ( i ) cq, i 1 ( i 1 ) 1 t w t w i N 7

8 Power Optimal Pipeline Main Idea: Passing available slack of some stages to more timing critical stages to provide them with more freedom in power optimization through voltage scaling For example, let T clk =T clk,min =560ps and t s =t h =t cq =30ps If FF1 is replaced with a SEFF with a window size of 50ps the first stage borrows 50ps from the second stage the circuit can be powered with a lower supply voltage level Ideally, 10% V dd reduction ->19% power saving C1 C2 C3 D Q D Q D Q D Q d1=500ps d2=400ps d3=450ps FF0 FF1 FF2 FF3 CLK 8

9 PSLP Problem Statement Power-optimal Soft Linear Pipeline Design Goal: Minimize the total power consumption of an N-stage linear pipeline circuit Variables: Optimal supply voltage level (1 variable) Transparency windows size of the individual soft-edge FF-sets (N-1) Delay elements to avoid hold time violations (N) Constraints: N N 1 N = total + Comb, i + FF, i i DE, i Setup/hold times i= 1 i= 1 i= 1 Window size limits st..() I d () v T t ( w, v) t ( w, v);1 i N i clk s, i i cq, i 1 i 1 Single supply voltage Min. P P ( v) P ( w, v) P ( z, v) ( II) δ ( v) + z t ( w, v) t ( w, v);1 i N i i hi, i cq, i 1 i 1 ( III) w w w ;1 i N 1 min i 0 1 max ( IV) v V, V..., Vm { } 1 i 9

10 SEFF Modeling Setup time, hold time, clock-to-q delay, and power dissipation i are functions of both voltage and ( ) transparency window size Voltage-dependent coefficients are determined from SPICE simulations tsi, ( wi, v) = a1( v) wi + a0( v) thi, wi, v = b1( v) wi + b0( v) tcq, i ( wi, v) = c1( v) wi + c0( v) 2 FF, i = 2 i + 1 i + 0 P d v w d v w d v ( ) ( ) ( ) Setup Tim me (ps) Vdd=0.9V Vdd=1.0V Vdd=1.1V Vdd=1.2V Hold Tim me (ps) Vdd=0.9V Vdd=1.0V Vdd=1.1V Vdd=1.2V -to-q de elay (ps) Vdd=0.9V Vdd=1.0V Vdd=1.1V Vdd=1.2V Transparency window (ps) Transparency window (ps) Transparency window (ps) 10

11 Combinational Circuit Modeling Total power consumption at voltage level, v: 2 3 v v P () v = P + P V V comb, i dyn, i leak, i 0 0 Max and Min combinational logic cell delays (calculated from the alpha power law): V0 V t di() v = di( V0 ) v V δ V V α 0 t i () v = δ i ( V 0 ) v V t t V α Power dissipation overhead of a delay element: DE (, ) ( ) P z v = k v z 11

12 Solving the PSLP To solve PSLP Enumerate all possible values for v PSLP with fixed voltage (PSLP-FV)) P comb,i terms drop out of the cost function Voltage constraint (IV) disappears All other timing and power parameters become only dependent on w i and z i variables For each fixed v, a quadratic program is set up and solved We must minimize a quadratic cost function subject to linear inequality constraints PSLP-FV can be solved optimally in polynomial time 12

13 Experimental Setup Hspice simulations were used to extract parameters that are needed for the problem formulation 65nm Predictive Technology Model (PTM) Nominal supply voltage 1.2V Die temperature 100 o C The SIS optimization package was used to synthesize a set of linear pipelines as test-bench circuits The MOSEK toolbox used to solve the mathematical optimization problem All results were collected on a 2.4GHz Pentium 4PC with 2GB memory 13

14 Benchmark Spec Testbench (max, min) stage delays at nominal Clock (# of stages) voltage (ps) freq. (GHz) TB1 (4) (320,140), (332,150), (308,150), 2.0 (320,170) TB2 (5) (320,140), (332,150), (308,150), (280,145), (320,170) 2.0 TB3 (3) (325, 150), (310,155), (219,160) 2.0 TB4 (5) (275,40), (235,40), (245,60), (275,50), 50) (275,70) 70) TB5 (4) (310,100), (245,40), (245,50), (245,60)

15 Experimental Results Using slack passing to minimize power without degrading performance TB Power Red. (%) Optimum Vdd (V) Optimum Window size (ps) TB , 49, 22 TB , 49, 46, 21 TB ,52 TB , 35, 35, 20 TB , 41, 36 - Area overhead: Utilizing slack passing to improve performance Negligible compared Testbench Performance to size of the rest of Improvement (%) the pipeline circuit TB1 14% - Runtime for all TB2 15% benchmarks: Less TB3 20% than one second TB4 5% TB5 10% 15

16 A Case Study: 34-bit Adder Problem: How to partition a 34-bit adder into 4 stages of pipeline to achieve maximum performance? D X Q D Q Y D Q bits FF0 FF1 bits FF2 Z bits D Q FF3 T bits D Q FF4 CLK Maximum Performance X+Y+Z+T=34 D Q C3 C4 C1 D Q C2 D Q D Q D Q FF0 FF1 FF2 FF3 FF4 CLK C1 C2 C3 D Q D Q D Q D Q FF0 9 FF1 FF2 FF3 C4 8 D Q FF4 CLK 16

17 A Case Study: 34-bit Adder Maximum Performance Configuration Vdd (V) Min Clock Period (ps) Power Consumption (mw)

18 A Case Study: 34-bit Adder Problem: How to partition a 34-bit adder into 4 stages of pipeline to achieve minimum power at target performance level? Minimum 2.0GHz Configuration Vdd (V) Power Consumption (MW)

19 Conclusion We presented a new technique to minimize the total power consumption of a linear pipeline circuit by utilizing soft-edge flip-flops and choosing the optimal supply voltage level for the pipeline We formulated the problem as a mathematical program and solved it efficiently Our experimental results demonstrate that this technique is quite effective in reducing the power consumption of a pipeline circuit under a performance constraint Future work will focus on problem of minimizing the energy cost of throughput in a linear pipeline p circuit with dynamic error detection and correction capability 19