EECS 427 Lecture 15: Timing, Latches, and Registers Reading: Chapter 7. EECS 427 F09 Lecture Reminders

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1 EECS 427 Lecture 15: Timing, Latches, and Registers Reading: Chapter 7 1 Reminders CA assignments CA7 is due Thursday at noon ECE Graduate Symposium Poster session in ECE Atrium on Friday HW4 (detailed proposal) is due Tuesday 11/17 (one day extension) You should have completed your schematic design and simulation and started block layouts by then Send your proposal (in Word or LaTeX) by to the Zhengya, cutoff time: 11:59 pm on 11/17 uiz 2 on Monday 11/23? Your chance to improve your performance in uiz 1 The other option: review session (problem solving, &A) on Monday 11/23 in class, uiz 2 on Tuesday 11/24 5:40 pm 7:00 pm during the discussion slot 2 1

2 Clock and data flow in the same direction Positive Clock Skew In clk R1 1 t clk1 Combinational logic delay T T + 3 R2 t clk t hld hold T : T + t cq,max + t logic,max + t su so T t cq,max + t logic,max + t su - t hold : t hold + t logic,min + t cq,min so t hold t logic,min + t cq,min - Positive skew: Improves performance, but makes t hold harder to meet. If t hold is not met (race conditions), the circuit malfunctions independent of the clock period! Irwin and Narayanan 3 Clock and data flow in opposite directions Negative Clock Skew In R1 1 2 t hold t clk1 T Combinational logic T - delay 4 3 R2 t clk2 clk T : T - t cq,max + t logic,max + t su so T t cq,max + t logic,max + t su + t hold : t hold - t logic,min + t cq,min so t hold t logic,min + t cq,min + Negative skew: egrades performance, but t hold is easier to meet (eliminating race conditions) Irwin and Narayanan 4 2

3 Jitter causes T to vary on a cycle-by-cycle basis Clock Jitter In R1 Combinational logic clk t clk T t jitter tjitter T : T - 2t jitter t cq,max + t logic,max + t su so T t cq,max + t logic,max + t su + 2t jitter t hold : t hold + 2t jitter t logic,min + t cq,min so t hold t logic,min + t cq,min -2t jitter Jitter directly reduces the performance of a sequential circuit Jitter makes race condition worse Irwin and Narayanan 5 Combined Impact of Skew and Jitter Constraints on the minimum clock period ( > 0) In R1 t clk1 t jitter Combinational logic T T + R2 t clk2 t jitter T t cq,max + t logic,max + t su - + 2t jitter t hold t logic,min + t cq,min 2t jitter Positive skew with jitter: egrades performance, and makes t hold even harder to meet. (The acceptable skew is reduced by jitter.) Irwin and Narayanan 6 3

4 Register Based Timing Logic delay Skew Clock-to- delay Flip -flop Logic T SU T Clk- Representation after M. Horowitz, VLSI Circuits Registers and ynamic Logic Logic delay T SU T SU T Clk- T Clk- Precharge Evaluate Logic delay Evaluate Precharge Registers are used only with static logic 8 4

5 Latch timing t - When data arrives to transparent latch Latch is a soft barrier Clk t Clk- When data arrives to closed latch ata has to be re-launched 9 omino Logic with Latch Timing Harris, JSSC

6 Master-Slave Register Multiplexer-based latch pair I 2 T 2 I 3 I 5 T 4 I 6 I 1 T 1 M I 4 T 3 11 Setup Time M 2.0 I 2 2 T 2 Volts Volts I 2 2 T M time (nsec) time (nsec) (a) T setup nsec (b) T setup nsec 12 6

7 Reduced Clock Load T 1 I 1 T 2 I 3 I 2 I 4 13 Avoiding Clock Overlap A X B (a) Schematic diagram (b) Overlapping clock pairs 14 7

8 ynamic Latch Static ynamic (charge-based) 15 C 2 MOS V V M 2 M 6 M 4 X M 8 M 3 C L1 M 7 C L2 M 1 M 5 Master Stage Slave Stage Keepers can be added to make circuit pseudo-static 16 8

9 Insensitive to Clock-Overlap V V V V M 2 M 6 M 2 M 6 0 M 4 0 X M 8 X 1 M 3 1 M 7 M 1 M 5 M 1 M 5 (a) (0-0) overlap (b) (1-1) overlap 17 TSPC V V V V Out In In Out Positive latch (transparent when = 1) Negative latch (transparent when = 0) 18 9

10 Including Logic in TSPC V V V V PUN In 1 In 2 In PN In 1 In 2 Example: logic inside the latch AN latch 19 TSPC Register V V V M 3 M 6 M 9 Y M 2 X M 5 M 8 M 1 M 4 M

11 Pulse-Triggered Latches Ways to design an edge-triggered gg sequential cell: Master-Slave Latches Pulse-Triggered Latch ata L1 L2 L ata Clk Clk Clk Clk Clk 21 Pulsed Latches V V G M 3 M 2 G M 6 M 5 V M P X G M 1 M 4 M N () (a) register (b) glitch generation G (c) glitch clock 22 11

12 Pulsed Latches Hybrid Latch Flip-flop (HLFF), AM K-6 and K-7 : P 3 x P 1 M 3 M 6 M 2 P 2 M 5 M 1 M 4 23 Hybrid Latch-FF Timing Volts time (ns) 24 12

13 Latch-Based Pipeline In F G Out C 1 C 2 C 3 Compute F compute G 25 13