Introduction. Simulation methodology. Simulation results

Transcription

1

2 Introduction Simulation methodology Simulation results Conclusion and Perspectives

3 Introduction Simulation methodology Simulation results Conclusion and Perspectives

4 Radiation induced particles Solar Flare Solar wind Energies from kev to 100MeV Coronal mass ejection Increase radiation robustness for Non-Volatile circuits

5 Radiation induced particles Asynchronous Communication Solar Flare Solar wind Energies from kev to 100MeV Coronal mass ejection Increase radiation robustness for Non-Volatile circuits

6 Radiation induced particles Asynchronous Communication Solar Flare Solar wind Energies from kev to 100MeV Coronal mass ejection Increase radiation robustness for Non-Volatile circuits Radiation Hardening Techniques/Process Philippe Roche, SOI to the rescue

7 Radiation induced particles Asynchronous Communication Solar Flare Solar wind Energies from kev to 100MeV Coronal mass ejection Non-Volatile Memory Increase radiation robustness for Non-Volatile circuits Radiation Hardening Techniques/Process Harold Hughes, Radiation studies of spin-transfer torque materials and devices Philippe Roche, SOI to the rescue

8 Introduction Simulation methodology Simulation results Conclusion and Perspectives

9 Synchronous Flip-Flop = Master latch & Slave latch Asynchronous Half-Buffer = 2 Muller cells & 1 logic gate D Master Latch Slave Latch Q In0 Lack C Out0 Rack CLK In1 C Out1 26 transistors 28 transistors 15 sensitive nodes 14 sensitive nodes Identical timing through transistor sizing Circuit type Flip-Flop NV STT Flip-Flop NV SOT Flip-Flop Half-Buffer NV STT Half-Buffer NV SOT Half-Buffer Number of Errors

10 I inj = Q inj τ 1 τ 2 t e τ 1 e t τ 2 Ferlet-Cavrois, V and Paillet, P and Gaillardin, and others, Statistical analysis of the charge collected in SOI and bulk devices under heavy lon and proton irradiation implications for digital SETs, Nuclear Science, IEEE Transactions on, 2006, vol. 53, no 6, pp where 2pC Q inj 2pC τ 1 = 150ps τ 2 = 50ps Sensitive nodes SN1 SN2 Q inj = 470fC I inj = 1,8mA Example of a particle injection

11 Introduction Simulation methodology Simulation results Conclusion and Perspectives

12 Current (ma) As the supply voltage increases, the amplitude of the induced pulse decreases. vdd = 0,9v vdd = 1,3v Time (ps) As the supply voltage increases the conductance of the transistors increases also. Use the highest supply voltage permitted by the technology for increasing the robustness toward radiation.

13 LVT transistors are more robust than vbb NMOS vbb PMOS RVT transistors. BB BB LVT transistors have a higher leakage than RVT, so the induced current pulses are evacuated quicker due to the lower resistance. Use LVT transistors for space applications.

14 RVT transistors: The number of errors decreased as vbb increased. LVT transistors: vbb has no effect on the number of errors. As vbb increases in RVT transistors, there response is boosted and the accumulated charges caused by particle strikes can be evacuated quicker. LVT already have a low vt so the accumulated vt can be evacuated quicker. Body biasing has no effect on hardening when using LVT transistors.

15 Introduction Simulation methodology Simulation results Conclusion and Perspectives

16 Total Number of simulations 2000 (Number of input combinations Number of Sensitive Nodes 2 = Number of simulations) The simulation results have demonstrated that using the highest supply voltage permitted by the technology, in conjunction with LVT transistors is the best option to harden systems at transistor level. Comparison of Synchronous and Asynchronous architectures in a pipeline Integration of MTJs in both Synchronous and Asynchronous Hardening by design (TMR, DMR) Architecture level studies

17