EE241 - Spring 2003 Advanced Digital Integrated Circuits

Transcription

1 EE241 - Spring 2003 Advanced Digital Integrated Circuits Lecture 16 Energy-Recovery Circuits SOI Technology and Circuits Optimal EDP Contours 1

2 Leakage and Switching ELk 2 = ESw Opt L ln d K tech α avg Optimal designs have high leakage current Adiabatic Circuits R t r C ADIABATIC CHARGING E = (RC/t r )CV 2 (for t r >> RC) Applying slow input slopes reduces E below CV 2 Useful for driving large capacitors (Buffers) Power reduction > 4 for pad drivers (1 MHz) ISI 2

3 Adiabatic Computing Basic Concepts When charging a capacitor through RC-network with a slowly changing ramp, power dissipation is reduced by reducing the slope of the ramp. No switch should ever be enabled when a voltage is over it Make sure every node is reset to the original stage before performing the next operation! reversible computing -> take energy back to the source -> ensure that state is known Adiabatic Computing Principles of storing and erasing information:» Energy dissipation of the combinational logic can be made arbitrarily small by operating the circuit slowly enough» Information can be loaded into memory circuits dissipating only arbitrarily small energy» Information can be copied with arbitrarily small energy» Erasing the last copy of a piece of information dissipates an irreducible finite amount of energy. Koller, Athas, PhysComp 92, Landauer, IBM J. ResDev 61 3

4 Six-Phase Charge Transfer One-bit delay Watkins, JSSC 12/67 Split-Level Charge Recovery Younis, Knight, IWLPD 94 4

5 Adiabatic Circuits A B C φ 0 φ 1 φ 2 Holding the inputs for the each stage until the output energy has been returned from Athas Reversible Pipelines Make return path different In clk Logic return logic Out C Problem: always results in CV th2 /2 loss! 5

6 Reversible Pipelines φ 1 φ 3 d in φ 0 φ 2 φ i d i-1 d i φ 0 hold reset φ 1 d i+1 retrun φ 2 φ 3 Partially Erasable Latches Pck V 0 M 1 M 2 F 1 F 1 Output stays at V th M 3 M 4 Stored energy is ½ CV th2, vs. ½ CV 2 How to use this? 6

7 Partially Erasable Latches Pck M 1 M 2 F 1 F 1 Pck Pck 1 Pck Pck 1 F0 M 5 M 3 M 4 M 6 F0 Requires 4-clocks for interfacing Denker, ISLPED 94 Single Pck + Auxiliary Clock Pck M 1 M 2 F µ 2. 4µ F µ 12. µ CX M 5 M 6 CX 2. 4µ 12. µ 2. 4µ 12. µ F µ 12. µ M 7 M 3 M µ 2. 4µ 12. µ 12. µ M µ 12. µ F0 Pck CX F0 F A B Maksimovic et al, ISLPED 97 7

8 Clock Generation L Pck Principle V DD 2 Clk Q R C Logic Implementation L V G 0 Pck 1 f c Clk F 0 F 1 F 1 F2 F n 1 V B Enable Ck 720µ 1. 2µ Q F 0 F 0 Stage 1 F 1 F 1 Stage 2 F2 F 2 Stage n F n F n Clk 2 Q Q CX CX Single Pck + Reference Voltages Cascading Gates: Kim, Papaefthymiou, ISLPED 98 8

9 Adiabatic µp Athas, et al, JSSC 12/97 Athas, et al, JSSC 11/00 Adiabatic µp 9

10 E-R Latch W/ dynamic logic W/ PTL Other Ideas Charge recycling bus» H. Yamauchi, et al, JSSC, 4/95 Adiabatic display driver» J. Ammer, ISSCC 99 Various examples of charge-recycling logic 10

11 Silicon on Insulator (SOI) References:» Chapter 5 by Shahidi, Assaderaghi, Antoniadis» K. Bernstein, N.J. Rohrer, SOI Circuit Design Concepts, Kluwer 2000.» K. Bernstein, ISSCC 00 SOI Tutorial» 2001 Microprocessor Design Workshop, lectures by C.T Chuang and R. Preston» Articles from Chandrakasan/Brodersen, IEEE Press SOI Transistor Bernstein, ISSCC 00 11

12 SOI Devices Partially depleted (PD)» Pros: Easier to manufacture (Si thickness) Scalable, tolerance to variations Decoupling V T from Si thickness» Cons: Floating body effects: I-V kink, parasitic bipolar effect Fully depleted (FD)» Pros: Significantly reduced floating body effects Sharper subthreshold S» Cons: V T is a function of the charge in the body varies Manufacturability, compatibility with bulk CMOS Soi Microprocessors Comp. Processor Freq. Technology Comment Source IBM 64b Power GHz PD/SOI 0.08 um Leff, 7LM Cu ISSCC 01 IBM 64b Power4 (Test Chip) 1.00 GHz PD/SOI 0.08 um Leff, 7LM Cu IEDM 99 IBM 64b Power GHz PD/SOI 0.08 um Leff, 7LM Cu Hot Chip 99 EE Times 99 IBM 64b PowerPC 660 MHz PD/SOI 0.08 um Leff, 7LM Cu Migration from 0.12 um Leff ISSCC 00 IBM 64b PowerPC 550 MHz PD/SOI 0.12 um Leff, 6LM Cu Bulk 450 MHz 0.12 um Leff ISSCC 99 IBM 32b PowerPC (PowerPC750) 580 MHz PD/SOI 0.12 um Leff, 6LM Cu Bulk 480 MHz 0.12 um Leff ISSCC 99 Samsung 64b DEC Alpha 600 MHz FD/SOI 0.25 um Lgate, 4LM Al Bulk 433 MHz 0.35 um Lgate ISSCC 99 DEC StrongArm-110 (Core Only) 230 MHz (Tester Limit) PD/SOI 0.35 um 20% Perf. Over Bulk IEDM 97 From C.T. Chuang 12

13 SOI Design Advantages:» Less Capacitance (~5-40%)» Lower power» Reduced effective V T, short channel effects, body effect» Layout simplicity (no wells, plugs, ) Disadvantages:» History-dependent timing» Increased device leakage» Body effect issues» Self heating» Decoupling capacitance SOI Timing Issues µs constants ps constants Courtesy of IEEE Press, New York

14 Floating Body Effects in PD SOI Neither S or D junction biased body floats. Effects: Threshold Variability Kink in output characteristics PD FD Floating Body Effects in PD SOI (cont d) Parasitic Bipolar Transistor 14

15 SOI Circuit Considerations Static circuits history-dependent delay First switch (often slowest) vs. second switch (often fastest) Bernstein, ISSCC 00 Initial State Initial input at low» nfet V B determined by back-to-back diodes» pfet V B at V DD initially» pfet V B before input falling transition determined by capacitive coupling Initial input at high» nfet V B at GND initially» nfet V B before input rising transition determined by capacitive coupling» pfet V B determined by back-to-back diodes 15

16 First Two Transitions Courtesy of IEEE Press, New York History-Dependent Delay Bernstein, ISSCC 00 16

17 History-Dependent Delay History-Dependent Delay Convergence to steady state Noise Margins! 17

18 Dynamic Circuits in SOI Dynamic History Bipolar effect Less charge sharing Parasitic Bipolar Dynamic lookahead adder Cumulative Effect of Parasitic Bipolar Current and Propagated Noise Cause Data Corruption after 3rd Stage in The Chain Parasitic Bipolar Current VDD VDD T7 T8 T9 T10 XC0 XPCH PCH C0 T5 T6 xci ci Propagated Noise from ND2 Previous Stage T1 T2 T3 gz gp gg ND1 T0 CLK VDD GND C.T. Chuang (M. Canada et al., ISSCC, 1999) 18

19 Pre-discharging Nodes Intermediate nodes discharged to prevent parasitic bipolar effect Bulk Design SOI Design CLK CLK X X A0 B0 Y OUT A0 B0 Y OUT A1 B1 A1 B1 C.T. Chuang (D. H. Allen et al., ISSCC, 1999) Dynamic Circuit Techniques Conditional Feedback CLK Setup Inputs during Precharge A B FB_L OUT Pre-discharge Intermediate Node Cross-connected Inputs (Stack swizzling) E F F E CLK Re-order Pulldown Tree C.T. Chuang (D. H. Allen et al., ISSCC, 1999) 19

20 Pass-Transistor Logic in SOI Inverter: Keeper: PTL in SOI (Assaderaghi 94): DTMOS Example: V T = 0.4V at 0 V; 0.17V at 0.5 V 20

21 DTMOS Body and gate tied together DTMOS ID vs. VDS for normal and DT operation 21

22 DTMOS Subthreshold currents for SOI NMOS and PMOS transistors with bodies grounded vs. DTMOS 0.5V SOI Pass-Gate Logic CPL Buffer type A Gate-body connection (GBC) Buffer type B Input-body connection (IBC) Fuse, et al, ISSCC 96 22

23 0.5V SOI Pass-Gate Logic 23